2013-04-23 05:23:47 +08:00
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/*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx53.dtsi"
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/ {
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model = "DENX M53EVK";
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compatible = "denx,imx53-m53evk", "fsl,imx53";
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memory {
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reg = <0x70000000 0x20000000>;
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};
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soc {
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display@di1 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 1>;
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interface-pix-fmt = "bgr666";
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_ipu_disp2>;
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2013-04-23 05:23:47 +08:00
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display-timings {
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800x480p60 {
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native-mode;
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clock-frequency = <31500000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <40>;
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hback-porch = <88>;
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hsync-len = <128>;
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vback-porch = <33>;
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vfront-porch = <9>;
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vsync-len = <3>;
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vsync-active = <1>;
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};
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};
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};
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 3000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_pin_gpio>;
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user1 {
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label = "user1";
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gpios = <&gpio2 8 0>;
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linux,default-trigger = "heartbeat";
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};
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user2 {
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label = "user2";
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gpios = <&gpio2 9 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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regulators {
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compatible = "simple-bus";
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2014-02-07 23:18:30 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-04-23 05:23:47 +08:00
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2014-02-07 23:18:30 +08:00
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reg_3p2v: regulator@0 {
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2013-04-23 05:23:47 +08:00
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compatible = "regulator-fixed";
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2014-02-07 23:18:30 +08:00
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reg = <0>;
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2013-04-23 05:23:47 +08:00
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regulator-name = "3P2V";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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regulator-always-on;
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};
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};
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sound {
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compatible = "fsl,imx53-m53evk-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx53-m53evk-sgtl5000";
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ssi-controller = <&ssi2>;
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audio-codec = <&sgtl5000>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"LINE_IN", "Line In Jack",
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"Headphone Jack", "HP_OUT",
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"Ext Spk", "LINE_OUT";
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mux-int-port = <2>;
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mux-ext-port = <4>;
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};
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};
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&audmux {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_audmux>;
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2013-04-23 05:23:47 +08:00
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_can1>;
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2013-04-23 05:23:47 +08:00
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_can2>;
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2013-04-23 05:23:47 +08:00
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_esdhc1>;
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2013-04-23 05:23:47 +08:00
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cd-gpios = <&gpio1 1 0>;
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wp-gpios = <&gpio1 9 0>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_fec>;
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2013-04-23 05:23:47 +08:00
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phy-mode = "rmii";
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_i2c1>;
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2013-04-23 05:23:47 +08:00
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status = "okay";
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sgtl5000: codec@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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VDDA-supply = <®_3p2v>;
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VDDIO-supply = <®_3p2v>;
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2013-11-14 18:18:58 +08:00
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clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
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2013-04-23 05:23:47 +08:00
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_i2c2>;
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2013-04-23 05:23:47 +08:00
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clock-frequency = <400000>;
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status = "okay";
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stmpe610@41 {
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compatible = "st,stmpe610";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x41>;
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id = <0>;
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blocks = <0x5>;
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interrupts = <6 0x0>;
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interrupt-parent = <&gpio7>;
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irq-trigger = <0x1>;
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stmpe_touchscreen {
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compatible = "stmpe,ts";
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reg = <0>;
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ts,sample-time = <4>;
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ts,mod-12b = <1>;
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ts,ref-sel = <0>;
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ts,adc-freq = <1>;
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ts,ave-ctrl = <3>;
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ts,touch-det-delay = <3>;
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ts,settling = <4>;
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ts,fraction-z = <7>;
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ts,i-drive = <1>;
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};
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};
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eeprom: eeprom@50 {
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compatible = "atmel,24c128";
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reg = <0x50>;
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pagesize = <32>;
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};
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rtc: rtc@68 {
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compatible = "stm,m41t62";
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reg = <0x68>;
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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2013-11-04 14:45:46 +08:00
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pinctrl-0 = <&pinctrl_i2c3>;
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2013-04-23 05:23:47 +08:00
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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2013-11-04 14:45:46 +08:00
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imx53-m53evk {
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2013-04-23 05:23:47 +08:00
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
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MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
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>;
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};
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led_pin_gpio: led_gpio@0 {
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fsl,pins = <
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MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
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MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
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>;
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};
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2013-11-04 14:45:46 +08:00
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
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MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
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MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
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MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
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MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
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>;
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};
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pinctrl_can2: can2grp {
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fsl,pins = <
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MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
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MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
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MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
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MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
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MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
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>;
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};
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pinctrl_ipu_disp2: ipudisp2grp {
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fsl,pins = <
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MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
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MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
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MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
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MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
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MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
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MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
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MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
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MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
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MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
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MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_nand: nandgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
|
|
|
|
|
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
|
|
|
|
|
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
|
|
|
|
|
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
|
|
|
|
|
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
|
|
|
|
|
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
|
|
|
|
|
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
|
|
|
|
|
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
|
|
|
|
|
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
|
|
|
|
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
|
|
|
|
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
|
|
|
|
|
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
|
|
|
|
|
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
|
|
|
|
|
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
|
|
|
|
|
>;
|
|
|
|
|
};
|
2013-04-23 05:23:47 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&nfc {
|
|
|
|
|
pinctrl-names = "default";
|
2013-11-04 14:45:46 +08:00
|
|
|
pinctrl-0 = <&pinctrl_nand>;
|
2013-04-23 05:23:47 +08:00
|
|
|
nand-bus-width = <8>;
|
|
|
|
|
nand-ecc-mode = "hw";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pwm1 {
|
|
|
|
|
pinctrl-names = "default";
|
2013-11-04 14:45:46 +08:00
|
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
2013-04-23 05:23:47 +08:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&ssi2 {
|
|
|
|
|
fsl,mode = "i2s-slave";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart1 {
|
|
|
|
|
pinctrl-names = "default";
|
2013-11-04 14:45:46 +08:00
|
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
2013-04-23 05:23:47 +08:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart2 {
|
|
|
|
|
pinctrl-names = "default";
|
2013-11-04 14:45:46 +08:00
|
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
2013-04-23 05:23:47 +08:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart3 {
|
|
|
|
|
pinctrl-names = "default";
|
2013-11-04 14:45:46 +08:00
|
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
2013-04-23 05:23:47 +08:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
