2017-05-24 22:10:34 +08:00
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/*
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* Copyright (C) 2017 Marvell
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <crypto/internal/hash.h>
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#include <crypto/internal/skcipher.h>
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#include "safexcel.h"
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static u32 max_rings = EIP197_MAX_RINGS;
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module_param(max_rings, uint, 0644);
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MODULE_PARM_DESC(max_rings, "Maximum number of rings to use.");
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static void eip197_trc_cache_init(struct safexcel_crypto_priv *priv)
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{
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u32 val, htable_offset;
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int i;
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/* Enable the record cache memory access */
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val = readl(priv->base + EIP197_CS_RAM_CTRL);
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val &= ~EIP197_TRC_ENABLE_MASK;
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val |= EIP197_TRC_ENABLE_0;
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writel(val, priv->base + EIP197_CS_RAM_CTRL);
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/* Clear all ECC errors */
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writel(0, priv->base + EIP197_TRC_ECCCTRL);
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/*
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* Make sure the cache memory is accessible by taking record cache into
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* reset.
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*/
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val = readl(priv->base + EIP197_TRC_PARAMS);
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val |= EIP197_TRC_PARAMS_SW_RESET;
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val &= ~EIP197_TRC_PARAMS_DATA_ACCESS;
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writel(val, priv->base + EIP197_TRC_PARAMS);
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/* Clear all records */
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for (i = 0; i < EIP197_CS_RC_MAX; i++) {
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u32 val, offset = EIP197_CLASSIFICATION_RAMS + i * EIP197_CS_RC_SIZE;
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writel(EIP197_CS_RC_NEXT(EIP197_RC_NULL) |
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EIP197_CS_RC_PREV(EIP197_RC_NULL),
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priv->base + offset);
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val = EIP197_CS_RC_NEXT(i+1) | EIP197_CS_RC_PREV(i-1);
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if (i == 0)
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val |= EIP197_CS_RC_PREV(EIP197_RC_NULL);
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else if (i == EIP197_CS_RC_MAX - 1)
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val |= EIP197_CS_RC_NEXT(EIP197_RC_NULL);
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writel(val, priv->base + offset + sizeof(u32));
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}
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/* Clear the hash table entries */
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htable_offset = EIP197_CS_RC_MAX * EIP197_CS_RC_SIZE;
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for (i = 0; i < 64; i++)
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writel(GENMASK(29, 0),
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priv->base + EIP197_CLASSIFICATION_RAMS + htable_offset + i * sizeof(u32));
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/* Disable the record cache memory access */
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val = readl(priv->base + EIP197_CS_RAM_CTRL);
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val &= ~EIP197_TRC_ENABLE_MASK;
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writel(val, priv->base + EIP197_CS_RAM_CTRL);
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/* Write head and tail pointers of the record free chain */
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val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) |
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EIP197_TRC_FREECHAIN_TAIL_PTR(EIP197_CS_RC_MAX - 1);
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writel(val, priv->base + EIP197_TRC_FREECHAIN);
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/* Configure the record cache #1 */
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val = EIP197_TRC_PARAMS2_RC_SZ_SMALL(EIP197_CS_TRC_REC_WC) |
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EIP197_TRC_PARAMS2_HTABLE_PTR(EIP197_CS_RC_MAX);
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writel(val, priv->base + EIP197_TRC_PARAMS2);
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/* Configure the record cache #2 */
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val = EIP197_TRC_PARAMS_RC_SZ_LARGE(EIP197_CS_TRC_LG_REC_WC) |
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EIP197_TRC_PARAMS_BLK_TIMER_SPEED(1) |
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EIP197_TRC_PARAMS_HTABLE_SZ(2);
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writel(val, priv->base + EIP197_TRC_PARAMS);
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}
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static void eip197_write_firmware(struct safexcel_crypto_priv *priv,
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const struct firmware *fw, u32 ctrl,
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u32 prog_en)
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{
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const u32 *data = (const u32 *)fw->data;
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u32 val;
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int i;
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/* Reset the engine to make its program memory accessible */
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writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR |
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EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR,
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priv->base + ctrl);
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/* Enable access to the program memory */
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writel(prog_en, priv->base + EIP197_PE_ICE_RAM_CTRL);
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/* Write the firmware */
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for (i = 0; i < fw->size / sizeof(u32); i++)
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writel(be32_to_cpu(data[i]),
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priv->base + EIP197_CLASSIFICATION_RAMS + i * sizeof(u32));
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/* Disable access to the program memory */
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writel(0, priv->base + EIP197_PE_ICE_RAM_CTRL);
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/* Release engine from reset */
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val = readl(priv->base + ctrl);
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val &= ~EIP197_PE_ICE_x_CTRL_SW_RESET;
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writel(val, priv->base + ctrl);
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}
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static int eip197_load_firmwares(struct safexcel_crypto_priv *priv)
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{
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const char *fw_name[] = {"ifpp.bin", "ipue.bin"};
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const struct firmware *fw[FW_NB];
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int i, j, ret = 0;
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u32 val;
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for (i = 0; i < FW_NB; i++) {
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ret = request_firmware(&fw[i], fw_name[i], priv->dev);
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if (ret) {
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dev_err(priv->dev,
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"Failed to request firmware %s (%d)\n",
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fw_name[i], ret);
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goto release_fw;
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}
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}
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/* Clear the scratchpad memory */
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val = readl(priv->base + EIP197_PE_ICE_SCRATCH_CTRL);
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val |= EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER |
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EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN |
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EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS |
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EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS;
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writel(val, priv->base + EIP197_PE_ICE_SCRATCH_CTRL);
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memset(priv->base + EIP197_PE_ICE_SCRATCH_RAM, 0,
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EIP197_NUM_OF_SCRATCH_BLOCKS * sizeof(u32));
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eip197_write_firmware(priv, fw[FW_IFPP], EIP197_PE_ICE_FPP_CTRL,
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EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN);
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eip197_write_firmware(priv, fw[FW_IPUE], EIP197_PE_ICE_PUE_CTRL,
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EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN);
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release_fw:
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for (j = 0; j < i; j++)
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release_firmware(fw[j]);
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return ret;
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}
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static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
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{
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u32 hdw, cd_size_rnd, val;
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int i;
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hdw = readl(priv->base + EIP197_HIA_OPTIONS);
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hdw &= GENMASK(27, 25);
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hdw >>= 25;
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cd_size_rnd = (priv->config.cd_size + (BIT(hdw) - 1)) >> hdw;
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for (i = 0; i < priv->config.rings; i++) {
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/* ring base address */
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writel(lower_32_bits(priv->ring[i].cdr.base_dma),
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
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writel(upper_32_bits(priv->ring[i].cdr.base_dma),
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 16) |
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priv->config.cd_size,
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_DESC_SIZE);
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writel(((EIP197_FETCH_COUNT * (cd_size_rnd << hdw)) << 16) |
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(EIP197_FETCH_COUNT * priv->config.cd_offset),
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_CFG);
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/* Configure DMA tx control */
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val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
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val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
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writel(val,
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_DMA_CFG);
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/* clear any pending interrupt */
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writel(GENMASK(5, 0),
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priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_STAT);
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}
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return 0;
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}
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static int safexcel_hw_setup_rdesc_rings(struct safexcel_crypto_priv *priv)
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{
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u32 hdw, rd_size_rnd, val;
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int i;
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hdw = readl(priv->base + EIP197_HIA_OPTIONS);
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hdw &= GENMASK(27, 25);
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hdw >>= 25;
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rd_size_rnd = (priv->config.rd_size + (BIT(hdw) - 1)) >> hdw;
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for (i = 0; i < priv->config.rings; i++) {
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/* ring base address */
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writel(lower_32_bits(priv->ring[i].rdr.base_dma),
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
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writel(upper_32_bits(priv->ring[i].rdr.base_dma),
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 16) |
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priv->config.rd_size,
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_DESC_SIZE);
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writel(((EIP197_FETCH_COUNT * (rd_size_rnd << hdw)) << 16) |
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(EIP197_FETCH_COUNT * priv->config.rd_offset),
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_CFG);
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/* Configure DMA tx control */
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val = EIP197_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS);
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val |= EIP197_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS);
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val |= EIP197_HIA_xDR_WR_RES_BUF | EIP197_HIA_xDR_WR_CTRL_BUG;
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writel(val,
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_DMA_CFG);
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/* clear any pending interrupt */
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writel(GENMASK(7, 0),
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priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_STAT);
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/* enable ring interrupt */
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val = readl(priv->base + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
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val |= EIP197_RDR_IRQ(i);
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writel(val, priv->base + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
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}
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return 0;
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}
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static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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{
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u32 version, val;
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int i, ret;
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/* Determine endianess and configure byte swap */
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version = readl(priv->base + EIP197_HIA_VERSION);
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val = readl(priv->base + EIP197_HIA_MST_CTRL);
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if ((version & 0xffff) == EIP197_HIA_VERSION_BE)
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val |= EIP197_MST_CTRL_BYTE_SWAP;
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else if (((version >> 16) & 0xffff) == EIP197_HIA_VERSION_LE)
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val |= (EIP197_MST_CTRL_NO_BYTE_SWAP >> 24);
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writel(val, priv->base + EIP197_HIA_MST_CTRL);
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/* Configure wr/rd cache values */
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writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
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EIP197_MST_CTRL_WD_CACHE(WR_CACHE_4BITS),
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priv->base + EIP197_MST_CTRL);
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/* Interrupts reset */
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/* Disable all global interrupts */
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writel(0, priv->base + EIP197_HIA_AIC_G_ENABLE_CTRL);
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/* Clear any pending interrupt */
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writel(GENMASK(31, 0), priv->base + EIP197_HIA_AIC_G_ACK);
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/* Data Fetch Engine configuration */
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/* Reset all DFE threads */
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writel(EIP197_DxE_THR_CTRL_RESET_PE,
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priv->base + EIP197_HIA_DFE_THR_CTRL);
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/* Reset HIA input interface arbiter */
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writel(EIP197_HIA_RA_PE_CTRL_RESET,
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priv->base + EIP197_HIA_RA_PE_CTRL);
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/* DMA transfer size to use */
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val = EIP197_HIA_DFE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(5) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(9);
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val |= EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(5) | EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(7);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);
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val |= EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS);
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writel(val, priv->base + EIP197_HIA_DFE_CFG);
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/* Leave the DFE threads reset state */
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writel(0, priv->base + EIP197_HIA_DFE_THR_CTRL);
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/* Configure the procesing engine thresholds */
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writel(EIP197_PE_IN_xBUF_THRES_MIN(5) | EIP197_PE_IN_xBUF_THRES_MAX(9),
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priv->base + EIP197_PE_IN_DBUF_THRES);
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writel(EIP197_PE_IN_xBUF_THRES_MIN(5) | EIP197_PE_IN_xBUF_THRES_MAX(7),
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priv->base + EIP197_PE_IN_TBUF_THRES);
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/* enable HIA input interface arbiter and rings */
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writel(EIP197_HIA_RA_PE_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
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priv->base + EIP197_HIA_RA_PE_CTRL);
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|
|
/* Data Store Engine configuration */
|
|
|
|
|
|
|
|
/* Reset all DSE threads */
|
|
|
|
writel(EIP197_DxE_THR_CTRL_RESET_PE,
|
|
|
|
priv->base + EIP197_HIA_DSE_THR_CTRL);
|
|
|
|
|
|
|
|
/* Wait for all DSE threads to complete */
|
|
|
|
while ((readl(priv->base + EIP197_HIA_DSE_THR_STAT) &
|
|
|
|
GENMASK(15, 12)) != GENMASK(15, 12))
|
|
|
|
;
|
|
|
|
|
|
|
|
/* DMA transfer size to use */
|
|
|
|
val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
|
|
|
|
val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
|
2017-06-15 15:56:19 +08:00
|
|
|
val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
|
2017-06-15 15:56:21 +08:00
|
|
|
val |= EIP197_HIA_DSE_CFG_ALLWAYS_BUFFERABLE;
|
2017-06-15 15:56:20 +08:00
|
|
|
val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
|
2017-05-24 22:10:34 +08:00
|
|
|
writel(val, priv->base + EIP197_HIA_DSE_CFG);
|
|
|
|
|
|
|
|
/* Leave the DSE threads reset state */
|
|
|
|
writel(0, priv->base + EIP197_HIA_DSE_THR_CTRL);
|
|
|
|
|
|
|
|
/* Configure the procesing engine thresholds */
|
|
|
|
writel(EIP197_PE_OUT_DBUF_THRES_MIN(7) | EIP197_PE_OUT_DBUF_THRES_MAX(8),
|
|
|
|
priv->base + EIP197_PE_OUT_DBUF_THRES);
|
|
|
|
|
|
|
|
/* Processing Engine configuration */
|
|
|
|
|
|
|
|
/* H/W capabilities selection */
|
|
|
|
val = EIP197_FUNCTION_RSVD;
|
|
|
|
val |= EIP197_PROTOCOL_ENCRYPT_ONLY | EIP197_PROTOCOL_HASH_ONLY;
|
|
|
|
val |= EIP197_ALG_AES_ECB | EIP197_ALG_AES_CBC;
|
|
|
|
val |= EIP197_ALG_SHA1 | EIP197_ALG_HMAC_SHA1;
|
|
|
|
val |= EIP197_ALG_SHA2;
|
|
|
|
writel(val, priv->base + EIP197_PE_EIP96_FUNCTION_EN);
|
|
|
|
|
|
|
|
/* Command Descriptor Rings prepare */
|
|
|
|
for (i = 0; i < priv->config.rings; i++) {
|
|
|
|
/* Clear interrupts for this ring */
|
|
|
|
writel(GENMASK(31, 0),
|
|
|
|
priv->base + EIP197_HIA_AIC_R_ENABLE_CLR(i));
|
|
|
|
|
|
|
|
/* Disable external triggering */
|
|
|
|
writel(0, priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_CFG);
|
|
|
|
|
|
|
|
/* Clear the pending prepared counter */
|
|
|
|
writel(EIP197_xDR_PREP_CLR_COUNT,
|
|
|
|
priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PREP_COUNT);
|
|
|
|
|
|
|
|
/* Clear the pending processed counter */
|
|
|
|
writel(EIP197_xDR_PROC_CLR_COUNT,
|
|
|
|
priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PROC_COUNT);
|
|
|
|
|
|
|
|
writel(0,
|
|
|
|
priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PREP_PNTR);
|
|
|
|
writel(0,
|
|
|
|
priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_PROC_PNTR);
|
|
|
|
|
|
|
|
writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset) << 2,
|
|
|
|
priv->base + EIP197_HIA_CDR(i) + EIP197_HIA_xDR_RING_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Result Descriptor Ring prepare */
|
|
|
|
for (i = 0; i < priv->config.rings; i++) {
|
|
|
|
/* Disable external triggering*/
|
|
|
|
writel(0, priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_CFG);
|
|
|
|
|
|
|
|
/* Clear the pending prepared counter */
|
|
|
|
writel(EIP197_xDR_PREP_CLR_COUNT,
|
|
|
|
priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PREP_COUNT);
|
|
|
|
|
|
|
|
/* Clear the pending processed counter */
|
|
|
|
writel(EIP197_xDR_PROC_CLR_COUNT,
|
|
|
|
priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PROC_COUNT);
|
|
|
|
|
|
|
|
writel(0,
|
|
|
|
priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PREP_PNTR);
|
|
|
|
writel(0,
|
|
|
|
priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_PROC_PNTR);
|
|
|
|
|
|
|
|
/* Ring size */
|
|
|
|
writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset) << 2,
|
|
|
|
priv->base + EIP197_HIA_RDR(i) + EIP197_HIA_xDR_RING_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable command descriptor rings */
|
|
|
|
writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
|
|
|
|
priv->base + EIP197_HIA_DFE_THR_CTRL);
|
|
|
|
|
|
|
|
/* Enable result descriptor rings */
|
|
|
|
writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
|
|
|
|
priv->base + EIP197_HIA_DSE_THR_CTRL);
|
|
|
|
|
|
|
|
/* Clear any HIA interrupt */
|
|
|
|
writel(GENMASK(30, 20), priv->base + EIP197_HIA_AIC_G_ACK);
|
|
|
|
|
|
|
|
eip197_trc_cache_init(priv);
|
|
|
|
|
|
|
|
ret = eip197_load_firmwares(priv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
safexcel_hw_setup_cdesc_rings(priv);
|
|
|
|
safexcel_hw_setup_rdesc_rings(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring)
|
2017-05-24 22:10:34 +08:00
|
|
|
{
|
|
|
|
struct crypto_async_request *req, *backlog;
|
|
|
|
struct safexcel_context *ctx;
|
|
|
|
struct safexcel_request *request;
|
2017-06-15 15:56:24 +08:00
|
|
|
int ret, nreq = 0, cdesc = 0, rdesc = 0, commands, results;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:27 +08:00
|
|
|
priv->ring[ring].need_dequeue = false;
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
do {
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_bh(&priv->ring[ring].queue_lock);
|
|
|
|
backlog = crypto_get_backlog(&priv->ring[ring].queue);
|
2017-06-15 15:56:26 +08:00
|
|
|
req = crypto_dequeue_request(&priv->ring[ring].queue);
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_unlock_bh(&priv->ring[ring].queue_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
if (!req)
|
|
|
|
goto finalize;
|
|
|
|
|
|
|
|
request = kzalloc(sizeof(*request), EIP197_GFP_FLAGS(*req));
|
2017-06-15 15:56:25 +08:00
|
|
|
if (!request) {
|
|
|
|
spin_lock_bh(&priv->ring[ring].queue_lock);
|
|
|
|
crypto_enqueue_request(&priv->ring[ring].queue, req);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].queue_lock);
|
|
|
|
|
|
|
|
priv->ring[ring].need_dequeue = true;
|
|
|
|
goto finalize;
|
|
|
|
}
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
ctx = crypto_tfm_ctx(req->tfm);
|
2017-06-15 15:56:24 +08:00
|
|
|
ret = ctx->send(req, ring, request, &commands, &results);
|
2017-05-24 22:10:34 +08:00
|
|
|
if (ret) {
|
|
|
|
kfree(request);
|
2017-06-15 15:56:25 +08:00
|
|
|
req->complete(req, ret);
|
2017-06-15 15:56:24 +08:00
|
|
|
priv->ring[ring].need_dequeue = true;
|
2017-06-15 15:56:25 +08:00
|
|
|
goto finalize;
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (backlog)
|
|
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
list_add_tail(&request->list, &priv->ring[ring].list);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].egress_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
cdesc += commands;
|
|
|
|
rdesc += results;
|
|
|
|
} while (nreq++ < EIP197_MAX_BATCH_SZ);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
finalize:
|
2017-06-15 15:56:24 +08:00
|
|
|
if (nreq == EIP197_MAX_BATCH_SZ)
|
|
|
|
priv->ring[ring].need_dequeue = true;
|
|
|
|
else if (!nreq)
|
2017-05-24 22:10:34 +08:00
|
|
|
return;
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_bh(&priv->ring[ring].lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
/* Configure when we want an interrupt */
|
|
|
|
writel(EIP197_HIA_RDR_THRESH_PKT_MODE |
|
|
|
|
EIP197_HIA_RDR_THRESH_PROC_PKT(nreq),
|
|
|
|
priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_THRESH);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
/* let the RDR know we have pending descriptors */
|
|
|
|
writel((rdesc * priv->config.rd_offset) << 2,
|
|
|
|
priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PREP_COUNT);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
/* let the CDR know we have pending descriptors */
|
|
|
|
writel((cdesc * priv->config.cd_offset) << 2,
|
|
|
|
priv->base + EIP197_HIA_CDR(ring) + EIP197_HIA_xDR_PREP_COUNT);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_unlock_bh(&priv->ring[ring].lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void safexcel_free_context(struct safexcel_crypto_priv *priv,
|
|
|
|
struct crypto_async_request *req,
|
|
|
|
int result_sz)
|
|
|
|
{
|
|
|
|
struct safexcel_context *ctx = crypto_tfm_ctx(req->tfm);
|
|
|
|
|
|
|
|
if (ctx->result_dma)
|
|
|
|
dma_unmap_single(priv->dev, ctx->result_dma, result_sz,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
|
|
|
if (ctx->cache) {
|
|
|
|
dma_unmap_single(priv->dev, ctx->cache_dma, ctx->cache_sz,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
kfree(ctx->cache);
|
|
|
|
ctx->cache = NULL;
|
|
|
|
ctx->cache_sz = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void safexcel_complete(struct safexcel_crypto_priv *priv, int ring)
|
|
|
|
{
|
|
|
|
struct safexcel_command_desc *cdesc;
|
|
|
|
|
|
|
|
/* Acknowledge the command descriptors */
|
|
|
|
do {
|
|
|
|
cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr);
|
|
|
|
if (IS_ERR(cdesc)) {
|
|
|
|
dev_err(priv->dev,
|
|
|
|
"Could not retrieve the command descriptor\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} while (!cdesc->last_seg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void safexcel_inv_complete(struct crypto_async_request *req, int error)
|
|
|
|
{
|
|
|
|
struct safexcel_inv_result *result = req->data;
|
|
|
|
|
|
|
|
if (error == -EINPROGRESS)
|
|
|
|
return;
|
|
|
|
|
|
|
|
result->error = error;
|
|
|
|
complete(&result->completion);
|
|
|
|
}
|
|
|
|
|
|
|
|
int safexcel_invalidate_cache(struct crypto_async_request *async,
|
|
|
|
struct safexcel_context *ctx,
|
|
|
|
struct safexcel_crypto_priv *priv,
|
|
|
|
dma_addr_t ctxr_dma, int ring,
|
|
|
|
struct safexcel_request *request)
|
|
|
|
{
|
|
|
|
struct safexcel_command_desc *cdesc;
|
|
|
|
struct safexcel_result_desc *rdesc;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
spin_lock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
|
|
|
|
/* Prepare command descriptor */
|
|
|
|
cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma);
|
|
|
|
if (IS_ERR(cdesc)) {
|
|
|
|
ret = PTR_ERR(cdesc);
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
cdesc->control_data.type = EIP197_TYPE_EXTENDED;
|
|
|
|
cdesc->control_data.options = 0;
|
|
|
|
cdesc->control_data.refresh = 0;
|
|
|
|
cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR;
|
|
|
|
|
|
|
|
/* Prepare result descriptor */
|
|
|
|
rdesc = safexcel_add_rdesc(priv, ring, true, true, 0, 0);
|
|
|
|
|
|
|
|
if (IS_ERR(rdesc)) {
|
|
|
|
ret = PTR_ERR(rdesc);
|
|
|
|
goto cdesc_rollback;
|
|
|
|
}
|
|
|
|
|
|
|
|
request->req = async;
|
|
|
|
goto unlock;
|
|
|
|
|
|
|
|
cdesc_rollback:
|
|
|
|
safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
|
|
|
|
|
|
|
|
unlock:
|
|
|
|
spin_unlock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void safexcel_handle_result_descriptor(struct safexcel_crypto_priv *priv,
|
|
|
|
int ring)
|
|
|
|
{
|
|
|
|
struct safexcel_request *sreq;
|
|
|
|
struct safexcel_context *ctx;
|
|
|
|
int ret, i, nreq, ndesc = 0;
|
|
|
|
bool should_complete;
|
|
|
|
|
|
|
|
nreq = readl(priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PROC_COUNT);
|
|
|
|
nreq >>= 24;
|
|
|
|
nreq &= GENMASK(6, 0);
|
|
|
|
if (!nreq)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < nreq; i++) {
|
|
|
|
spin_lock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
sreq = list_first_entry(&priv->ring[ring].list,
|
|
|
|
struct safexcel_request, list);
|
|
|
|
list_del(&sreq->list);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
|
|
|
|
ctx = crypto_tfm_ctx(sreq->req->tfm);
|
|
|
|
ndesc = ctx->handle_result(priv, ring, sreq->req,
|
|
|
|
&should_complete, &ret);
|
|
|
|
if (ndesc < 0) {
|
|
|
|
dev_err(priv->dev, "failed to handle result (%d)", ndesc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(EIP197_xDR_PROC_xD_PKT(1) |
|
|
|
|
EIP197_xDR_PROC_xD_COUNT(ndesc * priv->config.rd_offset),
|
|
|
|
priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_PROC_COUNT);
|
|
|
|
|
|
|
|
if (should_complete) {
|
|
|
|
local_bh_disable();
|
|
|
|
sreq->req->complete(sreq->req, ret);
|
|
|
|
local_bh_enable();
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(sreq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void safexcel_handle_result_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct safexcel_work_data *data =
|
|
|
|
container_of(work, struct safexcel_work_data, work);
|
|
|
|
struct safexcel_crypto_priv *priv = data->priv;
|
|
|
|
|
|
|
|
safexcel_handle_result_descriptor(priv, data->ring);
|
|
|
|
|
2017-06-15 15:56:27 +08:00
|
|
|
if (priv->ring[data->ring].need_dequeue)
|
2017-06-15 15:56:24 +08:00
|
|
|
safexcel_dequeue(data->priv, data->ring);
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
struct safexcel_ring_irq_data {
|
|
|
|
struct safexcel_crypto_priv *priv;
|
|
|
|
int ring;
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t safexcel_irq_ring(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct safexcel_ring_irq_data *irq_data = data;
|
|
|
|
struct safexcel_crypto_priv *priv = irq_data->priv;
|
|
|
|
int ring = irq_data->ring;
|
|
|
|
u32 status, stat;
|
|
|
|
|
|
|
|
status = readl(priv->base + EIP197_HIA_AIC_R_ENABLED_STAT(ring));
|
|
|
|
if (!status)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
/* RDR interrupts */
|
|
|
|
if (status & EIP197_RDR_IRQ(ring)) {
|
|
|
|
stat = readl(priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_STAT);
|
|
|
|
|
|
|
|
if (unlikely(stat & EIP197_xDR_ERR)) {
|
|
|
|
/*
|
|
|
|
* Fatal error, the RDR is unusable and must be
|
|
|
|
* reinitialized. This should not happen under
|
|
|
|
* normal circumstances.
|
|
|
|
*/
|
|
|
|
dev_err(priv->dev, "RDR: fatal error.");
|
|
|
|
} else if (likely(stat & EIP197_xDR_THRESH)) {
|
|
|
|
queue_work(priv->ring[ring].workqueue, &priv->ring[ring].work_data.work);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ACK the interrupts */
|
|
|
|
writel(stat & 0xff,
|
|
|
|
priv->base + EIP197_HIA_RDR(ring) + EIP197_HIA_xDR_STAT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ACK the interrupts */
|
|
|
|
writel(status, priv->base + EIP197_HIA_AIC_R_ACK(ring));
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_request_ring_irq(struct platform_device *pdev, const char *name,
|
|
|
|
irq_handler_t handler,
|
|
|
|
struct safexcel_ring_irq_data *ring_irq_priv)
|
|
|
|
{
|
|
|
|
int ret, irq = platform_get_irq_byname(pdev, name);
|
|
|
|
|
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "unable to get IRQ '%s'\n", name);
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, handler, 0,
|
|
|
|
dev_name(&pdev->dev), ring_irq_priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "unable to request IRQ %d\n", irq);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct safexcel_alg_template *safexcel_algs[] = {
|
|
|
|
&safexcel_alg_ecb_aes,
|
|
|
|
&safexcel_alg_cbc_aes,
|
|
|
|
&safexcel_alg_sha1,
|
|
|
|
&safexcel_alg_sha224,
|
|
|
|
&safexcel_alg_sha256,
|
|
|
|
&safexcel_alg_hmac_sha1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int safexcel_register_algorithms(struct safexcel_crypto_priv *priv)
|
|
|
|
{
|
|
|
|
int i, j, ret = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) {
|
|
|
|
safexcel_algs[i]->priv = priv;
|
|
|
|
|
|
|
|
if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
|
|
|
|
ret = crypto_register_skcipher(&safexcel_algs[i]->alg.skcipher);
|
|
|
|
else
|
|
|
|
ret = crypto_register_ahash(&safexcel_algs[i]->alg.ahash);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
for (j = 0; j < i; j++) {
|
|
|
|
if (safexcel_algs[j]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
|
|
|
|
crypto_unregister_skcipher(&safexcel_algs[j]->alg.skcipher);
|
|
|
|
else
|
|
|
|
crypto_unregister_ahash(&safexcel_algs[j]->alg.ahash);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void safexcel_unregister_algorithms(struct safexcel_crypto_priv *priv)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) {
|
|
|
|
if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
|
|
|
|
crypto_unregister_skcipher(&safexcel_algs[i]->alg.skcipher);
|
|
|
|
else
|
|
|
|
crypto_unregister_ahash(&safexcel_algs[i]->alg.ahash);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void safexcel_configure(struct safexcel_crypto_priv *priv)
|
|
|
|
{
|
|
|
|
u32 val, mask;
|
|
|
|
|
|
|
|
val = readl(priv->base + EIP197_HIA_OPTIONS);
|
|
|
|
val = (val & GENMASK(27, 25)) >> 25;
|
|
|
|
mask = BIT(val) - 1;
|
|
|
|
|
|
|
|
val = readl(priv->base + EIP197_HIA_OPTIONS);
|
|
|
|
priv->config.rings = min_t(u32, val & GENMASK(3, 0), max_rings);
|
|
|
|
|
|
|
|
priv->config.cd_size = (sizeof(struct safexcel_command_desc) / sizeof(u32));
|
|
|
|
priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
|
|
|
|
|
|
|
|
priv->config.rd_size = (sizeof(struct safexcel_result_desc) / sizeof(u32));
|
|
|
|
priv->config.rd_offset = (priv->config.rd_size + mask) & ~mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct resource *res;
|
|
|
|
struct safexcel_crypto_priv *priv;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
priv->dev = dev;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
priv->base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(priv->base)) {
|
|
|
|
dev_err(dev, "failed to get resource\n");
|
|
|
|
return PTR_ERR(priv->base);
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->clk = of_clk_get(dev->of_node, 0);
|
|
|
|
if (!IS_ERR(priv->clk)) {
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "unable to enable clk (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* The clock isn't mandatory */
|
|
|
|
if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
}
|
|
|
|
|
2017-06-23 22:05:25 +08:00
|
|
|
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
|
2017-05-24 22:10:34 +08:00
|
|
|
if (ret)
|
|
|
|
goto err_clk;
|
|
|
|
|
|
|
|
priv->context_pool = dmam_pool_create("safexcel-context", dev,
|
|
|
|
sizeof(struct safexcel_context_record),
|
|
|
|
1, 0);
|
|
|
|
if (!priv->context_pool) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
safexcel_configure(priv);
|
|
|
|
|
|
|
|
for (i = 0; i < priv->config.rings; i++) {
|
|
|
|
char irq_name[6] = {0}; /* "ringX\0" */
|
|
|
|
char wq_name[9] = {0}; /* "wq_ringX\0" */
|
|
|
|
int irq;
|
|
|
|
struct safexcel_ring_irq_data *ring_irq;
|
|
|
|
|
|
|
|
ret = safexcel_init_ring_descriptors(priv,
|
|
|
|
&priv->ring[i].cdr,
|
|
|
|
&priv->ring[i].rdr);
|
|
|
|
if (ret)
|
|
|
|
goto err_clk;
|
|
|
|
|
|
|
|
ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL);
|
|
|
|
if (!ring_irq) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
ring_irq->priv = priv;
|
|
|
|
ring_irq->ring = i;
|
|
|
|
|
|
|
|
snprintf(irq_name, 6, "ring%d", i);
|
|
|
|
irq = safexcel_request_ring_irq(pdev, irq_name, safexcel_irq_ring,
|
|
|
|
ring_irq);
|
|
|
|
|
|
|
|
if (irq < 0)
|
|
|
|
goto err_clk;
|
|
|
|
|
|
|
|
priv->ring[i].work_data.priv = priv;
|
|
|
|
priv->ring[i].work_data.ring = i;
|
|
|
|
INIT_WORK(&priv->ring[i].work_data.work, safexcel_handle_result_work);
|
|
|
|
|
|
|
|
snprintf(wq_name, 9, "wq_ring%d", i);
|
|
|
|
priv->ring[i].workqueue = create_singlethread_workqueue(wq_name);
|
|
|
|
if (!priv->ring[i].workqueue) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
crypto_init_queue(&priv->ring[i].queue,
|
|
|
|
EIP197_DEFAULT_RING_SIZE);
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
INIT_LIST_HEAD(&priv->ring[i].list);
|
|
|
|
spin_lock_init(&priv->ring[i].lock);
|
|
|
|
spin_lock_init(&priv->ring[i].egress_lock);
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_init(&priv->ring[i].queue_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
atomic_set(&priv->ring_used, 0);
|
|
|
|
|
|
|
|
ret = safexcel_hw_init(priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "EIP h/w init failed (%d)\n", ret);
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = safexcel_register_algorithms(priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to register algorithms (%d)\n", ret);
|
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_clk:
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int safexcel_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct safexcel_crypto_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
safexcel_unregister_algorithms(priv);
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
for (i = 0; i < priv->config.rings; i++)
|
|
|
|
destroy_workqueue(priv->ring[i].workqueue);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id safexcel_of_match_table[] = {
|
|
|
|
{ .compatible = "inside-secure,safexcel-eip197" },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static struct platform_driver crypto_safexcel = {
|
|
|
|
.probe = safexcel_probe,
|
|
|
|
.remove = safexcel_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "crypto-safexcel",
|
|
|
|
.of_match_table = safexcel_of_match_table,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(crypto_safexcel);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
|
|
|
|
MODULE_AUTHOR("Ofer Heifetz <oferh@marvell.com>");
|
|
|
|
MODULE_AUTHOR("Igal Liberman <igall@marvell.com>");
|
|
|
|
MODULE_DESCRIPTION("Support for SafeXcel cryptographic engine EIP197");
|
|
|
|
MODULE_LICENSE("GPL v2");
|