2014-08-10 02:10:21 +08:00
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#ifndef __NVIF_CLASS_H__
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#define __NVIF_CLASS_H__
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2015-11-08 08:18:19 +08:00
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/* these class numbers are made up by us, and not nvidia-assigned */
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2015-11-08 09:56:00 +08:00
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#define NVIF_CLASS_CONTROL /* if0001.h */ -1
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2015-11-08 08:18:19 +08:00
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#define NVIF_CLASS_PERFMON -2
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#define NVIF_CLASS_PERFDOM -3
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2015-11-08 08:34:50 +08:00
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#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4
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#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5
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#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6
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#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7
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2014-08-10 02:10:21 +08:00
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_DEVICE 0x00000080
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2014-08-10 02:10:24 +08:00
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#define NV_DMA_FROM_MEMORY 0x00000002
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#define NV_DMA_TO_MEMORY 0x00000003
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#define NV_DMA_IN_MEMORY 0x0000003d
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2015-03-26 07:18:32 +08:00
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#define FERMI_TWOD_A 0x0000902d
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2015-05-21 09:04:10 +08:00
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#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
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2015-03-26 07:18:32 +08:00
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#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
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#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
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2015-11-08 08:44:19 +08:00
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#define NV04_DISP /* cl0046.h */ 0x00000046
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2014-08-10 02:10:27 +08:00
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2015-11-08 09:28:26 +08:00
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#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
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#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
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#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
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#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
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#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
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#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
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#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
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#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
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#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
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#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
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#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
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2014-08-10 02:10:25 +08:00
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2015-11-08 08:44:19 +08:00
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#define NV50_DISP /* cl5070.h */ 0x00005070
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#define G82_DISP /* cl5070.h */ 0x00008270
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#define GT200_DISP /* cl5070.h */ 0x00008370
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#define GT214_DISP /* cl5070.h */ 0x00008570
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#define GT206_DISP /* cl5070.h */ 0x00008870
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#define GF110_DISP /* cl5070.h */ 0x00009070
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#define GK104_DISP /* cl5070.h */ 0x00009170
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#define GK110_DISP /* cl5070.h */ 0x00009270
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#define GM107_DISP /* cl5070.h */ 0x00009470
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#define GM204_DISP /* cl5070.h */ 0x00009570
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2014-08-10 02:10:27 +08:00
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2015-08-20 12:54:19 +08:00
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#define NV31_MPEG 0x00003174
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#define G82_MPEG 0x00008274
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2015-08-20 12:54:19 +08:00
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#define NV74_VP2 0x00007476
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2015-11-08 08:44:19 +08:00
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#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
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#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
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#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
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#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
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#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
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#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
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#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
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#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
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#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
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#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
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#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
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#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
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#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
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#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
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#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
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#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
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#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
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#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
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#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
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#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
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#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
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#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
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#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
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#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
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#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
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#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
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#define GM204_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
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#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
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#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
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#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
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#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
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2014-08-10 02:10:27 +08:00
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2015-11-08 08:15:09 +08:00
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#define FERMI_A /* cl9097.h */ 0x00009097
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#define FERMI_B /* cl9097.h */ 0x00009197
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#define FERMI_C /* cl9097.h */ 0x00009297
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2014-08-10 02:10:29 +08:00
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2015-11-08 08:15:09 +08:00
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#define KEPLER_A /* cl9097.h */ 0x0000a097
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#define KEPLER_B /* cl9097.h */ 0x0000a197
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#define KEPLER_C /* cl9097.h */ 0x0000a297
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2014-08-10 02:10:29 +08:00
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2015-11-08 08:15:09 +08:00
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#define MAXWELL_A /* cl9097.h */ 0x0000b097
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#define MAXWELL_B /* cl9097.h */ 0x0000b197
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2014-08-10 02:10:29 +08:00
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2015-08-20 12:54:19 +08:00
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#define NV74_BSP 0x000074b0
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2015-08-20 12:54:19 +08:00
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#define GT212_MSVLD 0x000085b1
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#define IGT21A_MSVLD 0x000086b1
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#define G98_MSVLD 0x000088b1
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#define GF100_MSVLD 0x000090b1
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#define GK104_MSVLD 0x000095b1
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#define GT212_MSPDEC 0x000085b2
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#define G98_MSPDEC 0x000088b2
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#define GF100_MSPDEC 0x000090b2
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#define GK104_MSPDEC 0x000095b2
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#define GT212_MSPPP 0x000085b3
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#define G98_MSPPP 0x000088b3
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#define GF100_MSPPP 0x000090b3
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#define G98_SEC 0x000088b4
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#define GT212_DMA 0x000085b5
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#define FERMI_DMA 0x000090b5
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2015-08-20 12:54:19 +08:00
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#define KEPLER_DMA_COPY_A 0x0000a0b5
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#define MAXWELL_DMA_COPY_A 0x0000b0b5
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2015-08-20 12:54:19 +08:00
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#define FERMI_DECOMPRESS 0x000090b8
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2014-08-10 02:10:30 +08:00
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#define FERMI_COMPUTE_A 0x000090c0
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#define FERMI_COMPUTE_B 0x000091c0
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#define KEPLER_COMPUTE_A 0x0000a0c0
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#define KEPLER_COMPUTE_B 0x0000a1c0
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#define MAXWELL_COMPUTE_A 0x0000b0c0
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2015-03-26 07:28:34 +08:00
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#define MAXWELL_COMPUTE_B 0x0000b1c0
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2014-08-10 02:10:30 +08:00
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2015-08-20 12:54:19 +08:00
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#define NV74_CIPHER 0x000074c1
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2014-08-10 02:10:21 +08:00
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2014-08-10 02:10:21 +08:00
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/*******************************************************************************
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* client
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******************************************************************************/
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#define NV_CLIENT_DEVLIST 0x00
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struct nv_client_devlist_v0 {
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__u8 version;
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__u8 count;
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__u8 pad02[6];
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__u64 device[];
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};
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2014-08-10 02:10:21 +08:00
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/*******************************************************************************
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* device
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******************************************************************************/
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2014-08-10 02:10:24 +08:00
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struct nv_device_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 device; /* device identifier, ~0 for client default */
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};
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2014-08-10 02:10:21 +08:00
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#define NV_DEVICE_V0_INFO 0x00
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2015-08-20 12:54:16 +08:00
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#define NV_DEVICE_V0_TIME 0x01
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2014-08-10 02:10:21 +08:00
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struct nv_device_info_v0 {
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__u8 version;
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#define NV_DEVICE_INFO_V0_IGP 0x00
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#define NV_DEVICE_INFO_V0_PCI 0x01
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#define NV_DEVICE_INFO_V0_AGP 0x02
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#define NV_DEVICE_INFO_V0_PCIE 0x03
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#define NV_DEVICE_INFO_V0_SOC 0x04
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__u8 platform;
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__u16 chipset; /* from NV_PMC_BOOT_0 */
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__u8 revision; /* from NV_PMC_BOOT_0 */
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#define NV_DEVICE_INFO_V0_TNT 0x01
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#define NV_DEVICE_INFO_V0_CELSIUS 0x02
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#define NV_DEVICE_INFO_V0_KELVIN 0x03
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#define NV_DEVICE_INFO_V0_RANKINE 0x04
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#define NV_DEVICE_INFO_V0_CURIE 0x05
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#define NV_DEVICE_INFO_V0_TESLA 0x06
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#define NV_DEVICE_INFO_V0_FERMI 0x07
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#define NV_DEVICE_INFO_V0_KEPLER 0x08
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#define NV_DEVICE_INFO_V0_MAXWELL 0x09
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__u8 family;
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__u8 pad06[2];
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__u64 ram_size;
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__u64 ram_user;
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2015-08-20 12:54:16 +08:00
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char chip[16];
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char name[64];
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2014-08-10 02:10:21 +08:00
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};
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2015-08-20 12:54:16 +08:00
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struct nv_device_time_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 time;
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};
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2014-08-10 02:10:24 +08:00
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/*******************************************************************************
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* context dma
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******************************************************************************/
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struct nv_dma_v0 {
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__u8 version;
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#define NV_DMA_V0_TARGET_VM 0x00
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#define NV_DMA_V0_TARGET_VRAM 0x01
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#define NV_DMA_V0_TARGET_PCI 0x02
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#define NV_DMA_V0_TARGET_PCI_US 0x03
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#define NV_DMA_V0_TARGET_AGP 0x04
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__u8 target;
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#define NV_DMA_V0_ACCESS_VM 0x00
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#define NV_DMA_V0_ACCESS_RD 0x01
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#define NV_DMA_V0_ACCESS_WR 0x02
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#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
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__u8 access;
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__u8 pad03[5];
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__u64 start;
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__u64 limit;
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/* ... chipset-specific class data */
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};
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struct nv50_dma_v0 {
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__u8 version;
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#define NV50_DMA_V0_PRIV_VM 0x00
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#define NV50_DMA_V0_PRIV_US 0x01
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#define NV50_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define NV50_DMA_V0_PART_VM 0x00
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#define NV50_DMA_V0_PART_256 0x01
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#define NV50_DMA_V0_PART_1KB 0x02
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__u8 part;
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#define NV50_DMA_V0_COMP_NONE 0x00
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#define NV50_DMA_V0_COMP_1 0x01
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#define NV50_DMA_V0_COMP_2 0x02
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#define NV50_DMA_V0_COMP_VM 0x03
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__u8 comp;
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#define NV50_DMA_V0_KIND_PITCH 0x00
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#define NV50_DMA_V0_KIND_VM 0x7f
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__u8 kind;
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__u8 pad05[3];
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};
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struct gf100_dma_v0 {
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__u8 version;
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#define GF100_DMA_V0_PRIV_VM 0x00
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#define GF100_DMA_V0_PRIV_US 0x01
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#define GF100_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define GF100_DMA_V0_KIND_PITCH 0x00
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#define GF100_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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2015-08-20 12:54:21 +08:00
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struct gf119_dma_v0 {
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2014-08-10 02:10:24 +08:00
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__u8 version;
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2015-08-20 12:54:21 +08:00
|
|
|
#define GF119_DMA_V0_PAGE_LP 0x00
|
|
|
|
|
#define GF119_DMA_V0_PAGE_SP 0x01
|
2014-08-10 02:10:24 +08:00
|
|
|
__u8 page;
|
2015-08-20 12:54:21 +08:00
|
|
|
#define GF119_DMA_V0_KIND_PITCH 0x00
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|
|
|
|
#define GF119_DMA_V0_KIND_VM 0xff
|
2014-08-10 02:10:24 +08:00
|
|
|
__u8 kind;
|
|
|
|
|
__u8 pad03[5];
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-10 02:10:24 +08:00
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
|
* perfmon
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
|
2015-06-08 04:40:17 +08:00
|
|
|
#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
|
|
|
|
|
#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
|
2015-06-08 04:40:24 +08:00
|
|
|
#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
|
2015-06-08 04:40:17 +08:00
|
|
|
|
|
|
|
|
struct nvif_perfmon_query_domain_v0 {
|
|
|
|
|
__u8 version;
|
|
|
|
|
__u8 id;
|
|
|
|
|
__u8 counter_nr;
|
|
|
|
|
__u8 iter;
|
2015-06-08 04:40:19 +08:00
|
|
|
__u16 signal_nr;
|
|
|
|
|
__u8 pad05[2];
|
2015-06-19 23:36:37 +08:00
|
|
|
char name[64];
|
2015-06-08 04:40:17 +08:00
|
|
|
};
|
2015-06-08 04:40:15 +08:00
|
|
|
|
|
|
|
|
struct nvif_perfmon_query_signal_v0 {
|
|
|
|
|
__u8 version;
|
2015-06-08 04:40:18 +08:00
|
|
|
__u8 domain;
|
2015-06-08 04:40:19 +08:00
|
|
|
__u16 iter;
|
2015-06-08 04:40:20 +08:00
|
|
|
__u8 signal;
|
2015-06-08 04:40:23 +08:00
|
|
|
__u8 source_nr;
|
|
|
|
|
__u8 pad05[2];
|
2015-06-08 04:40:15 +08:00
|
|
|
char name[64];
|
|
|
|
|
};
|
|
|
|
|
|
2015-06-08 04:40:24 +08:00
|
|
|
struct nvif_perfmon_query_source_v0 {
|
|
|
|
|
__u8 version;
|
|
|
|
|
__u8 domain;
|
|
|
|
|
__u8 signal;
|
|
|
|
|
__u8 iter;
|
|
|
|
|
__u8 pad04[4];
|
|
|
|
|
__u32 source;
|
|
|
|
|
__u32 mask;
|
|
|
|
|
char name[64];
|
|
|
|
|
};
|
|
|
|
|
|
2015-06-08 04:40:15 +08:00
|
|
|
|
|
|
|
|
/*******************************************************************************
|
2015-06-08 04:40:26 +08:00
|
|
|
* perfdom
|
2015-06-08 04:40:15 +08:00
|
|
|
******************************************************************************/
|
|
|
|
|
|
2015-06-08 04:40:26 +08:00
|
|
|
struct nvif_perfdom_v0 {
|
2014-08-10 02:10:24 +08:00
|
|
|
__u8 version;
|
2015-06-08 04:40:20 +08:00
|
|
|
__u8 domain;
|
2015-06-08 04:40:26 +08:00
|
|
|
__u8 mode;
|
|
|
|
|
__u8 pad03[1];
|
|
|
|
|
struct {
|
|
|
|
|
__u8 signal[4];
|
2015-06-08 04:40:27 +08:00
|
|
|
__u64 source[4][8];
|
2015-06-08 04:40:26 +08:00
|
|
|
__u16 logic_op;
|
|
|
|
|
} ctr[4];
|
2014-08-10 02:10:24 +08:00
|
|
|
};
|
|
|
|
|
|
2015-06-08 04:40:26 +08:00
|
|
|
#define NVIF_PERFDOM_V0_INIT 0x00
|
|
|
|
|
#define NVIF_PERFDOM_V0_SAMPLE 0x01
|
|
|
|
|
#define NVIF_PERFDOM_V0_READ 0x02
|
2015-06-08 04:40:25 +08:00
|
|
|
|
2015-06-08 04:40:26 +08:00
|
|
|
struct nvif_perfdom_init {
|
2015-06-08 04:40:25 +08:00
|
|
|
};
|
2014-08-10 02:10:24 +08:00
|
|
|
|
2015-06-08 04:40:26 +08:00
|
|
|
struct nvif_perfdom_sample {
|
2014-08-10 02:10:24 +08:00
|
|
|
};
|
|
|
|
|
|
2015-06-08 04:40:26 +08:00
|
|
|
struct nvif_perfdom_read_v0 {
|
2014-08-10 02:10:24 +08:00
|
|
|
__u8 version;
|
|
|
|
|
__u8 pad01[7];
|
2015-06-08 04:40:26 +08:00
|
|
|
__u32 ctr[4];
|
2014-08-10 02:10:24 +08:00
|
|
|
__u32 clk;
|
2015-06-08 04:40:26 +08:00
|
|
|
__u8 pad04[4];
|
2014-08-10 02:10:24 +08:00
|
|
|
};
|
2014-08-10 02:10:21 +08:00
|
|
|
#endif
|
