linux/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.

Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

Example:

	eccmgr: eccmgr@ffd08140 {
		compatible = "altr,socfpga-ecc-manager";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		l2-ecc@ffd08140 {
			compatible = "altr,socfpga-l2-ecc";
			reg = <0xffd08140 0x4>;
			interrupts = <0 36 1>, <0 37 1>;
		};

		ocram-ecc@ffd08144 {
			compatible = "altr,socfpga-ocram-ecc";
			reg = <0xffd08144 0x4>;
			iram = <&ocram>;
			interrupts = <0 178 1>, <0 179 1>;
		};
	};

Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.

Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
	containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg        : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

Example:

	eccmgr: eccmgr@ffd06000 {
		compatible = "altr,socfpga-a10-ecc-manager";
		altr,sysmgr-syscon = <&sysmgr>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ranges;

		l2-ecc@ffd06010 {
			compatible = "altr,socfpga-a10-l2-ecc";
			reg = <0xffd06010 0x4>;
			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
				     <32 IRQ_TYPE_LEVEL_HIGH>;
		};

		ocram-ecc@ff8c3000 {
			compatible = "altr,socfpga-a10-ocram-ecc";
			reg = <0xff8c3000 0x90>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
				     <33 IRQ_TYPE_LEVEL_HIGH> ;
		};
	};