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linux/drivers/pinctrl/samsung/pinctrl-samsung.h

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pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
/*
* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* http://www.linaro.org
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __PINCTRL_SAMSUNG_H
#define __PINCTRL_SAMSUNG_H
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
pinctrl: samsung: Use one GPIO chip per pin bank This patch modifies the pinctrl-samsung driver to register one GPIO chip per pin bank, instead of a single chip for all pin banks of the controller. It simplifies GPIO accesses a lot (constant time instead of looping through the list of banks to find the right one) and should have a good effect on performance of any bit-banging driver. In addition it allows to reference GPIO pins by a phandle to the bank node and a local pin offset inside of the bank (similar to previous gpiolib driver), which is more clear and readable than using indices relative to the whole pin controller. Example: device { /* ... */ gpios = <&gpk0 4 0>; /* ... */ }; Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:17 +08:00
#include <linux/gpio.h>
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
/* pinmux function number for pin as gpio output line */
pinctrl: exynos: Lock GPIOs as interrupts when used as EINTs Currently after configuring a GPIO pin as an interrupt related pinmux registers are changed, but there is no protection from calling gpio_direction_*() in a badly written driver, which would cause the same pinmux register to be reconfigured for regular input/output and this disabling interrupt capability of the pin. This patch addresses this issue by moving pinmux reconfiguration to .irq_{request,release}_resources() callback of irq_chip and calling gpio_lock_as_irq() helper to prevent reconfiguration of pin direction. Setting up a GPIO interrupt on Samsung SoCs is a two-step operation - in addition to trigger configuration in a dedicated register, the pinmux must be also reconfigured to GPIO interrupt, which is a different function than normal GPIO input, although I/O-wise they both behave in the same way and gpio_get_value() can be used on a pin configured as IRQ as well. Such design implies subtleties such as gpio_direction_input() not having to fail if a pin is already configured as an interrupt nor change the configuration to normal input. But the FLAG_USED_AS_IRQ set in gpiolib by gpio_lock_as_irq() is only used to check that gpio_direction_output() is not called, it's not used to prevent gpio_direction_input() to be called. So this is not a complete solution for Samsung SoCs but it's definitely a move in the right direction. Signed-off-by: Tomasz Figa <t.figa@samsung.com> [javier: use request resources instead of startup and expand commit message] Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-09 07:48:05 +08:00
#define FUNC_INPUT 0x0
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
#define FUNC_OUTPUT 0x1
/**
* enum pincfg_type - possible pin configuration types supported.
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
* @PINCFG_TYPE_FUNC: Function configuration.
* @PINCFG_TYPE_DAT: Pin value configuration.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @PINCFG_TYPE_PUD: Pull up/down configuration.
* @PINCFG_TYPE_DRV: Drive strength configuration.
* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
*/
enum pincfg_type {
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
PINCFG_TYPE_FUNC,
PINCFG_TYPE_DAT,
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
PINCFG_TYPE_PUD,
PINCFG_TYPE_DRV,
PINCFG_TYPE_CON_PDN,
PINCFG_TYPE_PUD_PDN,
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
PINCFG_TYPE_NUM
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/*
* pin configuration (pull up/down and drive strength) type and its value are
* packed together into a 16-bits. The upper 8-bits represent the configuration
* type and the lower 8-bits hold the value of the configuration type.
*/
#define PINCFG_TYPE_MASK 0xFF
#define PINCFG_VALUE_SHIFT 8
#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
PINCFG_VALUE_SHIFT)
/**
* enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts
* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts This patch reworks wake-up interrupt handling in pinctrl-exynos driver, so each pin bank, which provides wake-up interrupts, has its own IRQ domain. Information about whether given pin bank provides wake-up interrupts, how many and whether they are separate or muxed are parsed from device tree. It gives following advantages: - interrupts can be specified in device tree in a more readable way, e.g. : device { /* ... */ interrupt-parent = <&gpx2>; interrupts = <4 0>; /* ... */ }; - the amount and layout of interrupts is not hardcoded in the code anymore, but defined in SoC-specific structure - bank and pin of each wake-up interrupt can be easily identified, to allow operations, such as setting the pin to EINT function, from irq_set_type() callback Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:18 +08:00
* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
*
* Samsung GPIO controller groups all the available pins into banks. The pins
* in a pin bank can support external gpio interrupts or external wakeup
* interrupts or no interrupts at all. From a software perspective, the only
* difference between external gpio and external wakeup interrupts is that
* the wakeup interrupts can additionally wakeup the system if it is in
* suspended state.
*/
enum eint_type {
EINT_TYPE_NONE,
EINT_TYPE_GPIO,
EINT_TYPE_WKUP,
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts This patch reworks wake-up interrupt handling in pinctrl-exynos driver, so each pin bank, which provides wake-up interrupts, has its own IRQ domain. Information about whether given pin bank provides wake-up interrupts, how many and whether they are separate or muxed are parsed from device tree. It gives following advantages: - interrupts can be specified in device tree in a more readable way, e.g. : device { /* ... */ interrupt-parent = <&gpx2>; interrupts = <4 0>; /* ... */ }; - the amount and layout of interrupts is not hardcoded in the code anymore, but defined in SoC-specific structure - bank and pin of each wake-up interrupt can be easily identified, to allow operations, such as setting the pin to EINT function, from irq_set_type() callback Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:18 +08:00
EINT_TYPE_WKUP_MUX,
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
#define PIN_NAME_LENGTH 10
#define PIN_GROUP(n, p, f) \
{ \
.name = n, \
.pins = p, \
.num_pins = ARRAY_SIZE(p), \
.func = f \
}
#define PMX_FUNC(n, g) \
{ \
.name = n, \
.groups = g, \
.num_groups = ARRAY_SIZE(g), \
}
struct samsung_pinctrl_drv_data;
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
/**
* struct samsung_pin_bank_type: pin bank type description
* @fld_width: widths of configuration bitfields (0 if unavailable)
pinctrl: samsung: Remove hardcoded register offsets This patch replaces statically hardcoded register offsets of Exynos SoCs with an array of register offsets in samsung_pin_bank_type struct. Thanks to this change, support for SoCs with other set and order of registers can be added (e.g. S3C24xx and S3C64xx). Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:53 +08:00
* @reg_offset: offsets of configuration registers (don't care of width is 0)
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
*/
struct samsung_pin_bank_type {
u8 fld_width[PINCFG_TYPE_NUM];
pinctrl: samsung: Remove hardcoded register offsets This patch replaces statically hardcoded register offsets of Exynos SoCs with an array of register offsets in samsung_pin_bank_type struct. Thanks to this change, support for SoCs with other set and order of registers can be added (e.g. S3C24xx and S3C64xx). Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:53 +08:00
u8 reg_offset[PINCFG_TYPE_NUM];
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
};
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
/**
* struct samsung_pin_bank_data: represent a controller pin-bank (init data).
* @type: type of the bank (register offsets and bitfield widths)
* @pctl_offset: starting offset of the pin-bank registers.
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
* @pctl_res_idx: index of base address for pin-bank registers.
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
* @nr_pins: number of pins included in this bank.
* @eint_func: function to set in CON register to configure pin as EINT.
* @eint_type: type of the external interrupt supported by the bank.
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
*/
struct samsung_pin_bank_data {
const struct samsung_pin_bank_type *type;
u32 pctl_offset;
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
u8 pctl_res_idx;
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
u8 nr_pins;
u8 eint_func;
enum eint_type eint_type;
u32 eint_mask;
u32 eint_offset;
const char *name;
};
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
/**
* struct samsung_pin_bank: represent a controller pin-bank.
pinctrl: samsung: Split pin bank description into two structures This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:52 +08:00
* @type: type of the bank (register offsets and bitfield widths)
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
* @pctl_base: base address of the pin-bank registers
pinctrl: samsung: Fix a typo in pinctrl-samsung.h struct samsung_pin_bank does not have a member called reg_offset. It should be pctl_offset instead. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-12-10 08:45:55 +08:00
* @pctl_offset: starting offset of the pin-bank registers.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @nr_pins: number of pins included in this bank.
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
* @eint_base: base address of the pin-bank EINT registers.
pinctrl: Add pinctrl-s3c64xx driver This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:55 +08:00
* @eint_func: function to set in CON register to configure pin as EINT.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @eint_type: type of the external interrupt supported by the bank.
pinctrl: Add pinctrl-s3c64xx driver This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:55 +08:00
* @eint_mask: bit mask of pins which support EINT function.
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @name: name to be prefixed for each pin in this pin bank.
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
pinctrl: samsung: Match pin banks with their device nodes This patch is a preparation for converting the pinctrl-samsung driver to one GPIO chip and IRQ domain per bank. It binds banks defined by internal driver data with bank nodes in device tree. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:13 +08:00
* @of_node: OF node of the bank.
pinctrl: samsung: Hold pointer to driver data in bank struct This patch is a preparation for converting the pinctrl-samsung driver to one GPIO chip and IRQ domain per bank. It allows one having only a pointer to particular bank struct to access driver data struct. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:14 +08:00
* @drvdata: link to controller driver data
pinctrl: exynos: Use one IRQ domain per pin bank Instead of registering one IRQ domain for all pin banks of a pin controller, this patch implements registration of per-bank domains. At a cost of a little memory overhead (~2.5KiB for all GPIO interrupts of Exynos4x12) it simplifies driver code and device tree sources, because GPIO interrupts can be now specified per banks. Example: device { /* ... */ interrupt-parent = <&gpa1>; interrupts = <3 0>; /* ... */ }; Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:16 +08:00
* @irq_domain: IRQ domain of the bank.
pinctrl: samsung: Use one GPIO chip per pin bank This patch modifies the pinctrl-samsung driver to register one GPIO chip per pin bank, instead of a single chip for all pin banks of the controller. It simplifies GPIO accesses a lot (constant time instead of looping through the list of banks to find the right one) and should have a good effect on performance of any bit-banging driver. In addition it allows to reference GPIO pins by a phandle to the bank node and a local pin offset inside of the bank (similar to previous gpiolib driver), which is more clear and readable than using indices relative to the whole pin controller. Example: device { /* ... */ gpios = <&gpk0 4 0>; /* ... */ }; Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:17 +08:00
* @gpio_chip: GPIO chip of the bank.
* @grange: linux gpio pin range supported by this bank.
pinctrl: exynos: Generalize the eint16_31 demux code The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-10-09 21:54:29 +08:00
* @irq_chip: link to irq chip for external gpio and wakeup interrupts.
pinctrl: samsung: Protect bank registers with a spinlock Certain pin control registers can be accessed from different contexts, i.e. pinctrl, gpio and irq functions. This makes the locking provided by pin control core insufficient. This patch adds necessary locking using a per bank spinlock as it was done in the old Samsung GPIO driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:50 +08:00
* @slock: spinlock protecting bank registers
pinctrl: samsung: fix suspend/resume functionality The GPIO states need to be restored after s2r and this is not currently supported in the pinctrl driver. This patch saves the gpio states before suspend and restores them after resume. Saving and restoring is done very early using syscore_ops and must happen before pins are released from their powerdown state. Patch originally from Prathyush K <prathyush.k@samsung.com> but rewritten by Doug Anderson <dianders@chromium.org>. Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-17 12:33:18 +08:00
* @pm_save: saved register values during suspend
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
*/
struct samsung_pin_bank {
pinctrl: samsung: Constify samsung_pin_bank_type struct This structure is not intended to be modified at runtime and functions as constant data shared between multiple pin banks. This patch makes all instances of it constant across the driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:39 +08:00
const struct samsung_pin_bank_type *type;
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
void __iomem *pctl_base;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
u32 pctl_offset;
u8 nr_pins;
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
void __iomem *eint_base;
pinctrl: Add pinctrl-s3c64xx driver This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:55 +08:00
u8 eint_func;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
enum eint_type eint_type;
pinctrl: Add pinctrl-s3c64xx driver This patch adds pinctrl-s3c64xx driver which implements pin control interface for Samsung S3C64xx SoCs. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:55 +08:00
u32 eint_mask;
pinctrl: samsung: Include bank-specific eint offset in bank struct Some SoCs, like Exynos4x12, have non-sequential layout of EINT control registers and so current way of calculating register addresses does not work correctly for them. This patch adds eint_offset field to samsung_pin_bank struct and modifies the driver to use it instead of calculating the offsets from bank index. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:15 +08:00
u32 eint_offset;
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
const char *name;
u32 pin_base;
pinctrl: samsung: Allow per-bank SoC-specific private data This patch extends pin bank descriptor structure with SoC-specific private data field that allows SoC-specific drivers to store their own private data. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-18 00:24:31 +08:00
void *soc_priv;
pinctrl: samsung: Match pin banks with their device nodes This patch is a preparation for converting the pinctrl-samsung driver to one GPIO chip and IRQ domain per bank. It binds banks defined by internal driver data with bank nodes in device tree. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:13 +08:00
struct device_node *of_node;
pinctrl: samsung: Hold pointer to driver data in bank struct This patch is a preparation for converting the pinctrl-samsung driver to one GPIO chip and IRQ domain per bank. It allows one having only a pointer to particular bank struct to access driver data struct. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:14 +08:00
struct samsung_pinctrl_drv_data *drvdata;
pinctrl: exynos: Use one IRQ domain per pin bank Instead of registering one IRQ domain for all pin banks of a pin controller, this patch implements registration of per-bank domains. At a cost of a little memory overhead (~2.5KiB for all GPIO interrupts of Exynos4x12) it simplifies driver code and device tree sources, because GPIO interrupts can be now specified per banks. Example: device { /* ... */ interrupt-parent = <&gpa1>; interrupts = <3 0>; /* ... */ }; Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:16 +08:00
struct irq_domain *irq_domain;
pinctrl: samsung: Use one GPIO chip per pin bank This patch modifies the pinctrl-samsung driver to register one GPIO chip per pin bank, instead of a single chip for all pin banks of the controller. It simplifies GPIO accesses a lot (constant time instead of looping through the list of banks to find the right one) and should have a good effect on performance of any bit-banging driver. In addition it allows to reference GPIO pins by a phandle to the bank node and a local pin offset inside of the bank (similar to previous gpiolib driver), which is more clear and readable than using indices relative to the whole pin controller. Example: device { /* ... */ gpios = <&gpk0 4 0>; /* ... */ }; Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-11 16:11:17 +08:00
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
pinctrl: exynos: Generalize the eint16_31 demux code The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-10-09 21:54:29 +08:00
struct exynos_irq_chip *irq_chip;
pinctrl: samsung: Protect bank registers with a spinlock Certain pin control registers can be accessed from different contexts, i.e. pinctrl, gpio and irq functions. This makes the locking provided by pin control core insufficient. This patch adds necessary locking using a per bank spinlock as it was done in the old Samsung GPIO driver. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-19 05:31:50 +08:00
spinlock_t slock;
pinctrl: samsung: fix suspend/resume functionality The GPIO states need to be restored after s2r and this is not currently supported in the pinctrl driver. This patch saves the gpio states before suspend and restores them after resume. Saving and restoring is done very early using syscore_ops and must happen before pins are released from their powerdown state. Patch originally from Prathyush K <prathyush.k@samsung.com> but rewritten by Doug Anderson <dianders@chromium.org>. Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-17 12:33:18 +08:00
u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/**
* struct samsung_pin_ctrl: represent a pin controller.
* @pin_banks: list of pin banks included in this controller.
* @nr_banks: number of pin banks.
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
* @nr_ext_resources: number of the extra base address for pin banks.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @eint_gpio_init: platform specific callback to setup the external gpio
* interrupts for the controller.
* @eint_wkup_init: platform specific callback to setup the external wakeup
* interrupts for the controller.
*/
struct samsung_pin_ctrl {
pinctrl: samsung: Separate per-bank init and runtime data Currently the driver mixes constant init data with runtime data, which is far from being elegant and can invite potential hard to track issues. This patch intends to solve this by introducing a new samsung_pin_bank_data structure to hold only constant data known at compile time, which can be copied to main samsung_pin_bank struct used at runtime. In addition, thanks to this change, all per-bank initdata can be marked with const and __initconst keywords and dropped after init completes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:41 +08:00
const struct samsung_pin_bank_data *pin_banks;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
u32 nr_banks;
pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-11-09 16:40:10 +08:00
int nr_ext_resources;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
pinctrl: samsung: Add support for SoC-specific suspend/resume callbacks SoC-specific driver might require additional save and restore of registers. This patch adds pair of SoC-specific callbacks per pinctrl device to account for this. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-18 00:24:30 +08:00
void (*suspend)(struct samsung_pinctrl_drv_data *);
void (*resume)(struct samsung_pinctrl_drv_data *);
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/**
* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
pinctrl: samsung: fix suspend/resume functionality The GPIO states need to be restored after s2r and this is not currently supported in the pinctrl driver. This patch saves the gpio states before suspend and restores them after resume. Saving and restoring is done very early using syscore_ops and must happen before pins are released from their powerdown state. Patch originally from Prathyush K <prathyush.k@samsung.com> but rewritten by Doug Anderson <dianders@chromium.org>. Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-17 12:33:18 +08:00
* @node: global list node
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
* @pin_groups: list of pin groups available to the driver.
* @nr_groups: number of such pin groups.
* @pmx_functions: list of pin functions available to the driver.
* @nr_function: number of such pin functions.
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
* @pin_base: starting system wide pin number.
* @nr_pins: number of pins supported by the controller.
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
*/
struct samsung_pinctrl_drv_data {
pinctrl: samsung: fix suspend/resume functionality The GPIO states need to be restored after s2r and this is not currently supported in the pinctrl driver. This patch saves the gpio states before suspend and restores them after resume. Saving and restoring is done very early using syscore_ops and must happen before pins are released from their powerdown state. Patch originally from Prathyush K <prathyush.k@samsung.com> but rewritten by Doug Anderson <dianders@chromium.org>. Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-17 12:33:18 +08:00
struct list_head node;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
struct device *dev;
int irq;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
const struct samsung_pin_group *pin_groups;
unsigned int nr_groups;
const struct samsung_pmx_func *pmx_functions;
unsigned int nr_functions;
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
struct samsung_pin_bank *pin_banks;
u32 nr_banks;
unsigned int pin_base;
unsigned int nr_pins;
void (*suspend)(struct samsung_pinctrl_drv_data *);
void (*resume)(struct samsung_pinctrl_drv_data *);
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/**
* struct samsung_pin_group: represent group of pins of a pinmux function.
* @name: name of the pin group, used to lookup the group.
* @pins: the pins included in this group.
* @num_pins: number of pins included in this group.
* @func: the function number to be programmed when selected.
*/
struct samsung_pin_group {
const char *name;
const unsigned int *pins;
u8 num_pins;
u8 func;
};
/**
* struct samsung_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
* @num_groups: number of groups included in @groups.
*/
struct samsung_pmx_func {
const char *name;
const char **groups;
u8 num_groups;
pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes One of remaining limitations of current pinctrl-samsung driver was the inability to parse multiple pinmux/pinconf group nodes grouped inside a single device tree node. It made defining groups of pins for single purpose, but with different parameters very inconvenient. This patch implements Tegra-like support for grouping multiple pinctrl groups inside one device tree node, by completely changing the way pin groups and functions are parsed from device tree. The code creating pinctrl maps from DT nodes has been borrowed from pinctrl-tegra, while the initial creation of groups and functions has been completely rewritten with following assumptions: - each group consists of just one pin and does not depend on data from device tree, - each function is represented by a device tree child node of the pin controller, which in turn can contain multiple child nodes for pins that need to have different configuration values. Device Tree bindings are fully backwards compatible. New functionality can be used by defining a new pinctrl group consisting of several child nodes, as on following example: sd4_bus8: sd4-bus-width8 { part-1 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; samsung,pin-drv = <3>; }; part-2 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <4>; samsung,pin-pud = <4>; samsung,pin-drv = <3>; }; }; Tested on Exynos4210-Trats board and a custom Exynos4212-based one. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-02 23:41:03 +08:00
u32 val;
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
};
/* list of all exported SoC specific data */
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
pinctrl: exynos: Add support for Exynos4415 The pin controllers of Exynos4415 are similar to Exynos4412, but certain differences cause the need to create separate driver data for it. This patch adds pin controller and bank descriptor arrays to the driver to support the new SoC. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> [cw00.choi: Rebase it on mainline kernel] Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> [tomasz.figa@gmail.com: Resolved merge with earlier clean-up series.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-10-27 09:21:18 +08:00
extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[];
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
pinctrl: exynos: add exynos5410 SoC specific data Add Samsung EXYNOS5410 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5410. Signed-off-by: Hakjoo Kim <ruppi.kim@hardkernel.com> [AF: Rebased onto Exynos5260, irq_chip consolidation, const'ification] Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Tested-by: Pavel Fedin <p.fedin@samsung.com> [k.kozlowski: Rebased on current v4.3] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2015-03-16 06:00:32 +08:00
extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[];
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
pinctrl: exynos: Add support for Exynos5433 This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi- functional input/output port pins and 135 memory port pins. There are 41 general port groups and 2 memory port groups. Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-21 14:43:11 +08:00
extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[];
pinctrl: exynos: Add initial driver data for Exynos7 This patch adds initial driver data for Exynos7 pinctrl support. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-10-09 21:54:32 +08:00
extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];
pinctrl: samsung: Constify samsung_pin_ctrl struct In order to separate initialization constants from runtime data, this patch modifies the driver to store only constant data in samsung_pin_ctrl struct and copy data required at runtime to samsung_pinctrl_drv_data struct. This makes it possible to mark all existing instances of samsung_pin_ctrl struct as const and __initconst. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 03:05:40 +08:00
extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[];
extern const struct samsung_pin_ctrl s3c2416_pin_ctrl[];
extern const struct samsung_pin_ctrl s3c2440_pin_ctrl[];
extern const struct samsung_pin_ctrl s3c2450_pin_ctrl[];
extern const struct samsung_pin_ctrl s5pv210_pin_ctrl[];
pinctrl: add samsung pinctrl and gpiolib driver Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 05:07:19 +08:00
#endif /* __PINCTRL_SAMSUNG_H */