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linux/arch/arc/include/asm/arcregs.h

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ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
/*
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H
ARC: Interrupt Handling This contains: -bootup arch IRQ init: init_IRQ(), arc_init_IRQ() -generic IRQ subsystem glue: arch_do_IRQ() -basic IRQ chip setup for in-core intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:18 +08:00
/* Build Configuration Registers */
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
#define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#define ARC_REG_CRC_BCR 0x62
ARC: Interrupt Handling This contains: -bootup arch IRQ init: init_IRQ(), arc_init_IRQ() -generic IRQ subsystem glue: arch_do_IRQ() -basic IRQ chip setup for in-core intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:18 +08:00
#define ARC_REG_VECBASE_BCR 0x68
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#define ARC_REG_PERIBASE_BCR 0x69
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
#define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
ARCv2: MMUv4: cache programming model changes Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-04-06 19:53:57 +08:00
#define ARC_REG_SLC_BCR 0xce
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#define ARC_REG_AP_BCR 0x76
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#define ARC_REG_XY_MEM_BCR 0x79
#define ARC_REG_MAC_BCR 0x7a
#define ARC_REG_MUL_BCR 0x7b
#define ARC_REG_SWAP_BCR 0x7c
#define ARC_REG_NORM_BCR 0x7d
#define ARC_REG_MIXMAX_BCR 0x7e
#define ARC_REG_BARREL_BCR 0x7f
#define ARC_REG_D_UNCACH_BCR 0x6A
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#define ARC_REG_BPU_BCR 0xc0
#define ARC_REG_ISA_CFG_BCR 0xc1
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
#define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
ARC: Fix RTT boot printing Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-03-08 16:48:21 +08:00
#define ARC_REG_RTT_BCR 0xF2
ARCv2: [intc] HS38 core interrupt controller Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-03-06 16:38:20 +08:00
#define ARC_REG_IRQ_BCR 0xF3
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
#define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#define ARC_REG_SMART_BCR 0xFF
ARCv2: Support IO Coherency and permutations involving L1 and L2 caches In case of ARCv2 CPU there're could be following configurations that affect cache handling for data exchanged with peripherals via DMA: [1] Only L1 cache exists [2] Both L1 and L2 exist, but no IO coherency unit [3] L1, L2 caches and IO coherency unit exist Current implementation takes care of [1] and [2]. Moreover support of [2] is implemented with run-time check for SLC existence which is not super optimal. This patch introduces support of [3] and rework of DMA ops usage. Instead of doing run-time check every time a particular DMA op is executed we'll have 3 different implementations of DMA ops and select appropriate one during init. As for IOC support for it we need: [a] Implement empty DMA ops because IOC takes care of cache coherency with DMAed data [b] Route dma_alloc_coherent() via dma_alloc_noncoherent() This is required to make IOC work in first place and also serves as optimization as LD/ST to coherent buffers can be srviced from caches w/o going all the way to memory Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [vgupta: -Added some comments about IOC gains -Marked dma ops as static, -Massaged changelog a bit] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-05-26 00:54:28 +08:00
#define ARC_REG_CLUSTER_BCR 0xcf
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
#define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
ARC: Interrupt Handling This contains: -bootup arch IRQ init: init_IRQ(), arc_init_IRQ() -generic IRQ subsystem glue: arch_do_IRQ() -basic IRQ chip setup for in-core intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:18 +08:00
ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 reg It is better to use it instead of magic numbers. Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-01-31 19:45:21 +08:00
/* Common for ARCompact and ARCv2 status register */
#define ARC_REG_STATUS32 0x0A
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
/* status32 Bits Positions */
#define STATUS_AE_BIT 5 /* Exception active */
#define STATUS_DE_BIT 6 /* PC is in delay slot */
#define STATUS_U_BIT 7 /* User/Kernel mode */
ARC: change return value of userspace cmpxchg assist syscall The original syscall only used to return errno to indicate if cmpxchg succeeded. It was not returning the "previous" value which typical cmpxchg callers are interested in to build their slowpaths or retry loops. Given user preemption in syscall return path etc, it is not wise to check this in userspace afterwards, but should be what kernel actually observed in the syscall. So change the syscall interface to always return the previous value and additionally set Z flag to indicate whether operation succeeded or not (just like ARM implementation when they used to have this syscall) The flag approach avoids having to put_user errno which is nice given the use case for this syscall cares mostly about the "previous" value. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-08 02:36:46 +08:00
#define STATUS_Z_BIT 11
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
#define STATUS_L_BIT 12 /* Loop inhibit */
/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
#define STATUS_U_MASK (1<<STATUS_U_BIT)
ARC: change return value of userspace cmpxchg assist syscall The original syscall only used to return errno to indicate if cmpxchg succeeded. It was not returning the "previous" value which typical cmpxchg callers are interested in to build their slowpaths or retry loops. Given user preemption in syscall return path etc, it is not wise to check this in userspace afterwards, but should be what kernel actually observed in the syscall. So change the syscall interface to always return the previous value and additionally set Z flag to indicate whether operation succeeded or not (just like ARM implementation when they used to have this syscall) The flag approach avoids having to put_user errno which is nice given the use case for this syscall cares mostly about the "previous" value. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-08 02:36:46 +08:00
#define STATUS_Z_MASK (1<<STATUS_Z_BIT)
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
#define STATUS_L_MASK (1<<STATUS_L_BIT)
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
/*
* ECR: Exception Cause Reg bits-n-pieces
* [23:16] = Exception Vector
* [15: 8] = Exception Cause Code
* [ 7: 0] = Exception Parameters (for certain types only)
*/
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
#ifdef CONFIG_ISA_ARCOMPACT
ARC: cosmetic: Remove unused ECR bitfield masks Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-22 20:24:45 +08:00
#define ECR_V_MEM_ERR 0x01
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
#define ECR_V_INSN_ERR 0x02
#define ECR_V_MACH_CHK 0x20
#define ECR_V_ITLB_MISS 0x21
#define ECR_V_DTLB_MISS 0x22
#define ECR_V_PROTV 0x23
ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth values pt_regs->event was set with artificial values to identify the low level system event (syscall trap / breakpoint trap / exceptions / interrupts) With r8 saving out of the way, the full word can be used to save real ECR (Exception Cause Register) which helps idenify the event naturally, including additional info such as cause code, param. Only for Interrupts, where ECR is not applicable, do we resort to synthetic non ECR values. SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with different runtime values. The ptrace helpers now use the sub-fields of ECR to distinguish the events (e.g. vector 0x25 is trap, param 0 is syscall...) The following benefits will follow: (1) This centralizes the location of where ECR is saved and will allow the cleanup of task->thread.cause_code ECR placeholder which is set in non-uniform way. Then ARC VM code can safely rely on it being there for purpose of finer grained VM_EXEC dcache flush (based on exec fault: I-TLB Miss) (2) Further, ECR being passed around from low level handlers as arg can be eliminated as it is part of standard reg-file in pt_regs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-06-11 21:26:54 +08:00
#define ECR_V_TRAP 0x25
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
#else
#define ECR_V_MEM_ERR 0x01
#define ECR_V_INSN_ERR 0x02
#define ECR_V_MACH_CHK 0x03
#define ECR_V_ITLB_MISS 0x04
#define ECR_V_DTLB_MISS 0x05
#define ECR_V_PROTV 0x06
#define ECR_V_TRAP 0x09
#endif
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
ARC: cosmetic: Remove unused ECR bitfield masks Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-22 20:24:45 +08:00
/* DTLB Miss and Protection Violation Cause Codes */
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
#define ECR_C_PROTV_INST_FETCH 0x00
#define ECR_C_PROTV_LOAD 0x01
#define ECR_C_PROTV_STORE 0x02
#define ECR_C_PROTV_XCHG 0x03
#define ECR_C_PROTV_MISALIG_DATA 0x04
ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR values Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-28 17:54:30 +08:00
#define ECR_C_BIT_PROTV_MISALIG_DATA 10
/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB 0x01
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS 8
#define ECR_C_BIT_DTLB_ST_MISS 9
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
/* Auxiliary registers */
#define AUX_IDENTITY 4
ARCv2: boot log: identify HS48 cores (dual issue) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-22 09:02:44 +08:00
#define AUX_EXEC_CTRL 8
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
#define AUX_INTR_VEC_BASE 0x25
ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores HS release 3.0 provides for even more flexibility in specifying the volatile address space for mapping peripherals. With HS 2.1 @start was made flexible / programmable - with HS 3.0 even @end can be setup (vs. fixed to 0xFFFF_FFFF before). So add code to reflect that and while at it remove an unused struct defintion Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-08-27 06:41:29 +08:00
#define AUX_VOL 0x5e
ARC: MMU Context Management ARC700 MMU provides for tagging TLB entries with a 8-bit ASID to avoid having to flush the TLB every task switch. It also allows for a quick way to invalidate all the TLB entries for task useful for: * COW sementics during fork() * task exit()ing Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
ARC: Process-creation/scheduling/idle-loop Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:18 +08:00
/*
* Floating Pt Registers
* Status regs are read-only (build-time) so need not be saved/restored
*/
#define ARC_AUX_FP_STAT 0x300
#define ARC_AUX_DPFP_1L 0x301
#define ARC_AUX_DPFP_1H 0x302
#define ARC_AUX_DPFP_2L 0x303
#define ARC_AUX_DPFP_2H 0x304
#define ARC_AUX_DPFP_STAT 0x305
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
#ifndef __ASSEMBLY__
ARC: breakout aux handling into a separate header ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-01 02:09:34 +08:00
#include <soc/arc/aux.h>
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem init Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2013-01-18 17:42:20 +08:00
/* Helpers */
#define TO_KB(bytes) ((bytes) >> 10)
#define TO_MB(bytes) (TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
ARC: Process-creation/scheduling/idle-loop Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:18 +08:00
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
/*
***************************************************************
* Build Configuration Registers, with encoded hardware config
*/
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int chip_id:16, cpu_id:8, family:8;
#else
unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
ARC: boot log: decontaminate ARCv2 ISA_CONFIG register ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not compatible. cpuinfo_arc had isa info placeholder which was mashup of bits form both. Untangle this by defining it off of ARCv2 ISA info and it is fine even for ARC700 since former is a super set of latter (ARC700 buildonly has 2 bits for atomics and stack check). At runtime, we treat ARCv2 ISA info as a generic placeholder but populate it correctly depending on ARC700 or HS. This paves way for adding more HS specific bits in isa info which was colliding with the extra bits for arc700. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-22 08:46:38 +08:00
struct bcr_isa_arcv2 {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
ARC: boot log: decontaminate ARCv2 ISA_CONFIG register ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not compatible. cpuinfo_arc had isa info placeholder which was mashup of bits form both. Untangle this by defining it off of ARCv2 ISA info and it is fine even for ARC700 since former is a super set of latter (ARC700 buildonly has 2 bits for atomics and stack check). At runtime, we treat ARCv2 ISA info as a generic placeholder but populate it correctly depending on ARC700 or HS. This paves way for adding more HS specific bits in isa info which was colliding with the extra bits for arc700. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-22 08:46:38 +08:00
pad1:12, ver:8;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#else
ARC: boot log: decontaminate ARCv2 ISA_CONFIG register ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not compatible. cpuinfo_arc had isa info placeholder which was mashup of bits form both. Untangle this by defining it off of ARCv2 ISA info and it is fine even for ARC700 since former is a super set of latter (ARC700 buildonly has 2 bits for atomics and stack check). At runtime, we treat ARCv2 ISA info as a generic placeholder but populate it correctly depending on ARC700 or HS. This paves way for adding more HS specific bits in isa info which was colliding with the extra bits for arc700. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-22 08:46:38 +08:00
unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
ldd:1, pad2:4, div_rem:4;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#endif
};
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct bcr_mpy {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#else
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#endif
};
struct bcr_extn_xymem {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
#else
unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
#endif
};
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
struct bcr_iccm_arcompact {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int base:16, pad:5, sz:3, ver:8;
#else
unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
struct bcr_iccm_arcv2 {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#else
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#endif
};
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
struct bcr_dccm_arcompact {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int res:21, sz:3, ver:8;
#else
unsigned int ver:8, sz:3, res:21;
#endif
};
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
struct bcr_dccm_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
#else
unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
#endif
};
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
/* ARCompact: Both SP and DP FPU BCRs have same format */
struct bcr_fp_arcompact {
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int fast:1, ver:8;
#else
unsigned int ver:8, fast:1;
#endif
};
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
struct bcr_fp_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
#else
unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
#endif
};
ARC: breakout timer include code into separate header ... ... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-01 04:06:19 +08:00
#include <soc/arc/timers.h>
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct bcr_bpu_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
#else
unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
#endif
};
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
struct bcr_bpu_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
#else
unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
#endif
};
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
/* Error Protection Build: ECC/Parity */
struct bcr_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
#else
unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
#endif
};
/* Error Protection Control */
struct ctl_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
#else
unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
#endif
};
struct bcr_lpb {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:16, entries:8, ver:8;
#else
unsigned int ver:8, entries:8, pad:16;
#endif
};
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
unsigned int info:24, ver:8;
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#else
ARCv2: boot report CCMs (Closely Coupled Memories) - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-16 15:06:18 +08:00
unsigned int ver:8, info:24;
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
#endif
};
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
/*
*******************************************************************
* Generic structures to hold build configuration used at runtime
*/
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
struct cpuinfo_arc_mmu {
ARC: boot log: decode more mmu config items Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-02 21:54:20 +08:00
unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
ARC: mm: compute TLB size as needed from ways * sets This frees up some bits to hold more high level info such as PAE being present, w/o increasing the size of already bloated cpuinfo struct Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-02 14:55:35 +08:00
unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
};
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
struct cpuinfo_arc_cache {
ARC: mm: No need to save cache version in @cpuinfo Historical MMU revisions have been paired with Cache revision updates which are captured in MMU and Cache Build Configuration Registers respectively. This was used in boot code to check for configurations mismatches, speically in simulations (such as running with non existent caches, non pairing MMU and Cache version etc). This can instead be inferred from other cache params such as line size. So remove @ver from post processed @cpuinfo which could be used later to save soem other interesting info. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-12-20 03:24:08 +08:00
unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
};
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct cpuinfo_arc_bpu {
unsigned int ver, full, num_cache, num_pred;
};
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
struct cpuinfo_arc_ccm {
unsigned int base_addr, sz;
};
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
struct cpuinfo_arc {
ARCv2: MMUv4: cache programming model changes Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-04-06 19:53:57 +08:00
struct cpuinfo_arc_cache icache, dcache, slc;
ARC: MMU Exception Handling * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
struct cpuinfo_arc_mmu mmu;
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct cpuinfo_arc_bpu bpu;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
struct bcr_identity core;
ARC: boot log: decontaminate ARCv2 ISA_CONFIG register ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not compatible. cpuinfo_arc had isa info placeholder which was mashup of bits form both. Untangle this by defining it off of ARCv2 ISA info and it is fine even for ARC700 since former is a super set of latter (ARC700 buildonly has 2 bits for atomics and stack check). At runtime, we treat ARCv2 ISA info as a generic placeholder but populate it correctly depending on ARC700 or HS. This paves way for adding more HS specific bits in isa info which was colliding with the extra bits for arc700. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-22 08:46:38 +08:00
struct bcr_isa_arcv2 isa;
ARC: boot log: refactor cpu name/release printing The motivation is to identify ARC750 vs. ARC770 (we currently print generic "ARC700"). A given ARC700 release could be 750 or 770, with same ARCNUM (or family identifier which is unfortunate). The existing arc_cpu_tbl[] kept a single concatenated string for core name and release which thus doesn't work for 750 vs. 770 identification. So split this into 2 tables, one with core names and other with release. And while we are at it, get rid of the range checking for family numbers. We just document the known to exist cores running Linux and ditch others. With this in place, we add detection of ARC750 which is - cores 0x33 and before - cores 0x34 and later with MMUv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-10-28 05:33:19 +08:00
const char *details, *name;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
unsigned int vec_base;
struct cpuinfo_arc_ccm iccm, dccm;
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
struct {
ARC: boot log: don't assume SWAPE instruction support This came to light when helping a customer with oldish ARC750 core who were getting instruction errors because of lack of SWAPE but boot log was incorrectly printing it as being present Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-10-21 09:08:10 +08:00
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-11 04:40:00 +08:00
fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
debug:1, ap:1, smart:1, rtt:1, pad3:4,
ARC: shrink cpuinfo by not saving full timer BCR Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-01-22 17:50:18 +08:00
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
ARC: boot: cpu feature print enhancements Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-09-25 19:24:43 +08:00
} extn;
struct bcr_mpy extn_mpy;
ARC: Boot #2: Verbose Boot reporting / feature verification Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:24 +08:00
struct bcr_extn_xymem extn_xymem;
ARC: Cache Flush Management * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-01-18 17:42:19 +08:00
};
extern struct cpuinfo_arc cpuinfo_arc700[];
ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
static inline int is_isa_arcv2(void)
{
return IS_ENABLED(CONFIG_ISA_ARCV2);
}
static inline int is_isa_arcompact(void)
{
return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
}
ARC: irqflags - Interrupt enabling/disabling at in-core intc ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
2013-01-18 17:42:16 +08:00
#endif /* __ASEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */