2019-05-27 14:55:01 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2005-09-26 14:04:21 +08:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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* PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*/
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2011-07-23 06:24:23 +08:00
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#include <linux/export.h>
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2005-09-26 14:04:21 +08:00
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/gfp.h>
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2005-09-26 14:04:21 +08:00
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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2018-10-31 06:09:49 +08:00
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#include <linux/memblock.h>
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2005-09-26 14:04:21 +08:00
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#include <linux/highmem.h>
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#include <linux/initrd.h>
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#include <linux/pagemap.h>
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2007-05-08 17:25:00 +08:00
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#include <linux/suspend.h>
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2009-10-27 03:24:31 +08:00
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#include <linux/hugetlb.h>
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2011-11-02 22:56:12 +08:00
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#include <linux/slab.h>
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2014-10-14 19:17:47 +08:00
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#include <linux/vmalloc.h>
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2017-06-28 09:32:33 +08:00
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#include <linux/memremap.h>
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2005-09-26 14:04:21 +08:00
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#include <asm/pgalloc.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/btext.h>
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#include <asm/tlb.h>
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2005-10-06 10:23:33 +08:00
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#include <asm/sections.h>
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2008-07-01 09:30:06 +08:00
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#include <asm/sparsemem.h>
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2005-10-10 19:58:35 +08:00
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#include <asm/vdso.h>
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2008-04-23 21:05:20 +08:00
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#include <asm/fixmap.h>
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2010-03-16 21:16:25 +08:00
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#include <asm/swiotlb.h>
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2011-12-02 20:26:23 +08:00
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#include <asm/rtas.h>
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2005-09-26 14:04:21 +08:00
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2019-03-29 17:59:59 +08:00
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#include <mm/mmu_decl.h>
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2005-09-26 14:04:21 +08:00
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#ifndef CPU_FTR_COHERENT_ICACHE
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#define CPU_FTR_COHERENT_ICACHE 0 /* XXX for now */
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#define CPU_FTR_NOEXECUTE 0
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#endif
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2012-08-21 09:42:33 +08:00
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unsigned long long memory_limit;
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2018-09-14 09:14:11 +08:00
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bool init_mem_is_free;
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2005-10-06 10:23:33 +08:00
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2008-04-23 21:05:20 +08:00
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#ifdef CONFIG_HIGHMEM
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pte_t *kmap_pte;
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2013-03-10 11:22:39 +08:00
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EXPORT_SYMBOL(kmap_pte);
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2008-04-23 21:05:20 +08:00
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pgprot_t kmap_prot;
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EXPORT_SYMBOL(kmap_prot);
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static inline pte_t *virt_to_kpte(unsigned long vaddr)
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{
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return pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr),
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vaddr), vaddr), vaddr);
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}
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#endif
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2005-10-29 08:46:18 +08:00
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pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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2005-09-26 14:04:21 +08:00
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unsigned long size, pgprot_t vma_prot)
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{
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if (ppc_md.phys_mem_access_prot)
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2005-10-29 08:46:18 +08:00
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return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
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2005-09-26 14:04:21 +08:00
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2005-10-29 08:46:18 +08:00
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if (!page_is_ram(pfn))
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2008-12-19 03:13:51 +08:00
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vma_prot = pgprot_noncached(vma_prot);
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2005-09-26 14:04:21 +08:00
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return vma_prot;
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}
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EXPORT_SYMBOL(phys_mem_access_prot);
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2005-10-31 10:37:12 +08:00
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#ifdef CONFIG_MEMORY_HOTPLUG
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2006-06-27 17:53:30 +08:00
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#ifdef CONFIG_NUMA
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int memory_add_physaddr_to_nid(u64 start)
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{
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return hot_add_scn_to_nid(start);
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}
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#endif
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2018-02-13 23:08:22 +08:00
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int __weak create_section_mapping(unsigned long start, unsigned long end, int nid)
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2016-07-05 13:07:54 +08:00
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{
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return -ENODEV;
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}
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int __weak remove_section_mapping(unsigned long start, unsigned long end)
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{
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return -ENODEV;
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}
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2019-11-04 10:32:57 +08:00
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#define FLUSH_CHUNK_SIZE SZ_1G
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/**
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* flush_dcache_range_chunked(): Write any modified data cache blocks out to
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* memory and invalidate them, in chunks of up to FLUSH_CHUNK_SIZE
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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* @chunk: the max size of the chunks
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*/
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static void flush_dcache_range_chunked(unsigned long start, unsigned long stop,
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unsigned long chunk)
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{
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unsigned long i;
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for (i = start; i < stop; i += chunk) {
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flush_dcache_range(i, min(stop, start + chunk));
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cond_resched();
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}
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}
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2019-05-14 08:21:26 +08:00
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int __ref arch_add_memory(int nid, u64 start, u64 size,
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struct mhp_restrictions *restrictions)
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2005-10-31 10:37:12 +08:00
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{
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unsigned long start_pfn = start >> PAGE_SHIFT;
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unsigned long nr_pages = size >> PAGE_SHIFT;
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2016-02-09 11:32:42 +08:00
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int rc;
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2005-10-31 10:37:12 +08:00
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2016-12-09 08:07:38 +08:00
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resize_hpt_for_hotplug(memblock_phys_mem_size());
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2006-03-22 15:00:05 +08:00
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start = (unsigned long)__va(start);
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2018-02-13 23:08:22 +08:00
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rc = create_section_mapping(start, start + size, nid);
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2016-02-09 11:32:42 +08:00
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if (rc) {
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2016-10-25 12:00:08 +08:00
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pr_warn("Unable to create mapping for hot added memory 0x%llx..0x%llx: %d\n",
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2016-02-09 11:32:42 +08:00
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start, start + size, rc);
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return -EFAULT;
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}
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2019-11-04 10:32:57 +08:00
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2019-05-14 08:21:26 +08:00
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return __add_pages(nid, start_pfn, nr_pages, restrictions);
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2005-10-31 10:37:12 +08:00
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}
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2013-02-23 08:32:58 +08:00
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2019-05-14 08:21:46 +08:00
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void __ref arch_remove_memory(int nid, u64 start, u64 size,
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2019-03-30 13:43:45 +08:00
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struct vmem_altmap *altmap)
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2013-02-23 08:32:58 +08:00
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{
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unsigned long start_pfn = start >> PAGE_SHIFT;
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unsigned long nr_pages = size >> PAGE_SHIFT;
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2019-06-26 20:27:13 +08:00
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struct page *page = pfn_to_page(start_pfn) + vmem_altmap_offset(altmap);
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2014-01-28 00:54:06 +08:00
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int ret;
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2013-02-23 08:32:58 +08:00
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2019-05-14 08:21:46 +08:00
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__remove_pages(page_zone(page), start_pfn, nr_pages, altmap);
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2014-10-14 19:17:47 +08:00
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/* Remove htab bolted mappings for this section of memory */
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start = (unsigned long)__va(start);
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2019-11-04 10:32:57 +08:00
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flush_dcache_range_chunked(start, start + size, FLUSH_CHUNK_SIZE);
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2014-10-14 19:17:47 +08:00
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ret = remove_section_mapping(start, start + size);
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2019-05-14 08:21:46 +08:00
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WARN_ON_ONCE(ret);
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2014-10-14 19:17:47 +08:00
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/* Ensure all vmalloc mappings are flushed in case they also
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* hit that section of memory
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*/
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vm_unmap_aliases();
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2014-01-28 00:54:06 +08:00
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2019-03-13 18:25:28 +08:00
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if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
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pr_warn("Hash collision while resizing HPT\n");
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2013-02-23 08:32:58 +08:00
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}
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#endif
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2008-02-05 16:10:18 +08:00
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2005-10-06 10:23:33 +08:00
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#ifndef CONFIG_NEED_MULTIPLE_NODES
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2018-02-13 23:08:16 +08:00
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void __init mem_topology_setup(void)
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2005-10-06 10:23:33 +08:00
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{
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2010-07-12 12:36:09 +08:00
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max_low_pfn = max_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
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2014-09-17 20:15:33 +08:00
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min_low_pfn = MEMORY_START >> PAGE_SHIFT;
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2005-10-06 10:23:33 +08:00
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#ifdef CONFIG_HIGHMEM
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2008-04-16 03:52:22 +08:00
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max_low_pfn = lowmem_end_addr >> PAGE_SHIFT;
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2005-10-06 10:23:33 +08:00
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#endif
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2013-01-09 20:40:18 +08:00
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/* Place all memblock_regions in the same node and merge contiguous
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* memblock_regions
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*/
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2018-06-15 06:28:02 +08:00
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memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
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2018-02-13 23:08:16 +08:00
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}
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2006-09-27 16:49:49 +08:00
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2018-02-13 23:08:16 +08:00
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void __init initmem_init(void)
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{
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2005-10-06 10:23:33 +08:00
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/* XXX need to clip this if using highmem? */
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2006-09-27 16:49:49 +08:00
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sparse_memory_present_with_active_regions(0);
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2014-09-17 20:15:36 +08:00
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sparse_init();
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2005-10-06 10:23:33 +08:00
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}
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2007-05-08 17:25:00 +08:00
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/* mark pages that don't exist as nosave */
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static int __init mark_nonram_nosave(void)
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{
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2010-08-04 11:43:53 +08:00
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struct memblock_region *reg, *prev = NULL;
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for_each_memblock(memory, reg) {
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if (prev &&
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2010-10-13 05:07:09 +08:00
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memblock_region_memory_end_pfn(prev) < memblock_region_memory_base_pfn(reg))
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register_nosave_region(memblock_region_memory_end_pfn(prev),
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memblock_region_memory_base_pfn(reg));
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2010-08-04 11:43:53 +08:00
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prev = reg;
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2007-05-08 17:25:00 +08:00
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}
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return 0;
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}
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2014-09-19 03:05:02 +08:00
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#else /* CONFIG_NEED_MULTIPLE_NODES */
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static int __init mark_nonram_nosave(void)
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{
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return 0;
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}
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#endif
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2007-05-08 17:25:00 +08:00
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2014-08-09 07:40:42 +08:00
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/*
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2018-12-17 00:53:49 +08:00
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* Zones usage:
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*
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* We setup ZONE_DMA to be 31-bits on all platforms and ZONE_NORMAL to be
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* everything else. GFP_DMA32 page allocations automatically fall back to
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* ZONE_DMA.
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*
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* By using 31-bit unconditionally, we can exploit ARCH_ZONE_DMA_BITS to
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* inform the generic DMA mapping code. 32-bit only devices (if not handled
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* by an IOMMU anyway) will take a first dip into ZONE_NORMAL and get
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* otherwise served by ZONE_DMA.
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2014-08-09 07:40:42 +08:00
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*/
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2018-12-17 00:53:49 +08:00
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static unsigned long max_zone_pfns[MAX_NR_ZONES];
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2014-08-09 07:40:42 +08:00
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2005-10-06 10:23:33 +08:00
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/*
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* paging_init() sets up the page tables - in fact we've already done this.
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*/
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void __init paging_init(void)
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{
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2011-07-05 02:44:19 +08:00
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unsigned long long total_ram = memblock_phys_mem_size();
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2010-07-12 12:36:09 +08:00
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phys_addr_t top_of_ram = memblock_end_of_DRAM();
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2005-10-06 10:23:33 +08:00
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#ifdef CONFIG_HIGHMEM
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2018-10-09 21:51:45 +08:00
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map_kernel_page(PKMAP_BASE, 0, __pgprot(0)); /* XXX gross */
|
2008-04-23 21:05:20 +08:00
|
|
|
pkmap_page_table = virt_to_kpte(PKMAP_BASE);
|
|
|
|
|
|
|
|
kmap_pte = virt_to_kpte(__fix_to_virt(FIX_KMAP_BEGIN));
|
2005-10-06 10:23:33 +08:00
|
|
|
kmap_prot = PAGE_KERNEL;
|
|
|
|
#endif /* CONFIG_HIGHMEM */
|
|
|
|
|
2011-07-05 02:44:19 +08:00
|
|
|
printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
|
2008-07-31 11:51:42 +08:00
|
|
|
(unsigned long long)top_of_ram, total_ram);
|
2006-04-13 04:25:01 +08:00
|
|
|
printk(KERN_DEBUG "Memory hole size: %ldMB\n",
|
2008-07-09 23:09:23 +08:00
|
|
|
(long int)((top_of_ram - total_ram) >> 20));
|
2014-08-09 07:40:42 +08:00
|
|
|
|
2018-12-17 00:53:49 +08:00
|
|
|
#ifdef CONFIG_ZONE_DMA
|
2019-06-13 16:24:46 +08:00
|
|
|
max_zone_pfns[ZONE_DMA] = min(max_low_pfn,
|
2019-06-25 22:17:27 +08:00
|
|
|
1UL << (ARCH_ZONE_DMA_BITS - PAGE_SHIFT));
|
2018-12-17 00:53:49 +08:00
|
|
|
#endif
|
|
|
|
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
|
2005-10-06 10:23:33 +08:00
|
|
|
#ifdef CONFIG_HIGHMEM
|
2018-12-17 00:53:49 +08:00
|
|
|
max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
|
2006-09-27 16:49:49 +08:00
|
|
|
#endif
|
2018-12-17 00:53:49 +08:00
|
|
|
|
2006-09-27 16:49:49 +08:00
|
|
|
free_area_init_nodes(max_zone_pfns);
|
2007-05-08 17:25:00 +08:00
|
|
|
|
|
|
|
mark_nonram_nosave();
|
2005-10-06 10:23:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init mem_init(void)
|
|
|
|
{
|
2013-10-12 08:22:38 +08:00
|
|
|
/*
|
|
|
|
* book3s is limited to 16 page sizes due to encoding this in
|
|
|
|
* a 4-bit field for slices.
|
|
|
|
*/
|
|
|
|
BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
|
|
|
|
|
2010-03-16 21:16:25 +08:00
|
|
|
#ifdef CONFIG_SWIOTLB
|
2012-08-03 18:14:10 +08:00
|
|
|
swiotlb_init(0);
|
2010-03-16 21:16:25 +08:00
|
|
|
#endif
|
|
|
|
|
2005-10-06 10:23:33 +08:00
|
|
|
high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
|
2013-07-04 06:04:32 +08:00
|
|
|
set_max_mapnr(max_pfn);
|
2018-10-31 06:09:30 +08:00
|
|
|
memblock_free_all();
|
2005-10-06 10:23:33 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
{
|
|
|
|
unsigned long pfn, highmem_mapnr;
|
|
|
|
|
2008-04-16 03:52:22 +08:00
|
|
|
highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
|
2005-10-06 10:23:33 +08:00
|
|
|
for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
|
2011-06-28 17:54:46 +08:00
|
|
|
phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
|
2005-10-06 10:23:33 +08:00
|
|
|
struct page *page = pfn_to_page(pfn);
|
2013-07-04 06:04:09 +08:00
|
|
|
if (!memblock_is_reserved(paddr))
|
|
|
|
free_highmem_page(page);
|
2005-10-06 10:23:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_HIGHMEM */
|
|
|
|
|
2011-06-29 03:54:47 +08:00
|
|
|
#if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
|
|
|
|
/*
|
|
|
|
* If smp is enabled, next_tlbcam_idx is initialized in the cpu up
|
|
|
|
* functions.... do it here for the non-smp case.
|
|
|
|
*/
|
|
|
|
per_cpu(next_tlbcam_idx, smp_processor_id()) =
|
|
|
|
(mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
|
|
|
|
#endif
|
|
|
|
|
2013-07-04 06:04:09 +08:00
|
|
|
mem_init_print_info(NULL);
|
2009-05-27 11:44:50 +08:00
|
|
|
#ifdef CONFIG_PPC32
|
|
|
|
pr_info("Kernel virtual memory layout:\n");
|
2019-04-27 00:23:32 +08:00
|
|
|
#ifdef CONFIG_KASAN
|
|
|
|
pr_info(" * 0x%08lx..0x%08lx : kasan shadow mem\n",
|
|
|
|
KASAN_SHADOW_START, KASAN_SHADOW_END);
|
|
|
|
#endif
|
2009-05-27 11:44:50 +08:00
|
|
|
pr_info(" * 0x%08lx..0x%08lx : fixmap\n", FIXADDR_START, FIXADDR_TOP);
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
|
|
|
pr_info(" * 0x%08lx..0x%08lx : highmem PTEs\n",
|
|
|
|
PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP));
|
|
|
|
#endif /* CONFIG_HIGHMEM */
|
powerpc/mm: don't display empty early ioremap area
On the 8xx, the layout displayed at boot is:
[ 0.000000] Memory: 121856K/131072K available (5728K kernel code, 592K rwdata, 1248K rodata, 560K init, 448K bss, 9216K reserved, 0K cma-reserved)
[ 0.000000] Kernel virtual memory layout:
[ 0.000000] * 0xffefc000..0xffffc000 : fixmap
[ 0.000000] * 0xffefc000..0xffefc000 : early ioremap
[ 0.000000] * 0xc9000000..0xffefc000 : vmalloc & ioremap
[ 0.000000] SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Remove display of an empty early ioremap.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/f6267226038cb25a839b567319e240576e3f8565.1565793287.git.christophe.leroy@c-s.fr
2019-08-14 22:36:10 +08:00
|
|
|
if (ioremap_bot != IOREMAP_TOP)
|
|
|
|
pr_info(" * 0x%08lx..0x%08lx : early ioremap\n",
|
|
|
|
ioremap_bot, IOREMAP_TOP);
|
2009-05-27 11:44:50 +08:00
|
|
|
pr_info(" * 0x%08lx..0x%08lx : vmalloc & ioremap\n",
|
|
|
|
VMALLOC_START, VMALLOC_END);
|
|
|
|
#endif /* CONFIG_PPC32 */
|
2005-10-06 10:23:33 +08:00
|
|
|
}
|
|
|
|
|
2011-06-18 15:36:39 +08:00
|
|
|
void free_initmem(void)
|
|
|
|
{
|
2011-06-18 15:36:40 +08:00
|
|
|
ppc_md.progress = ppc_printk_progress;
|
2017-07-14 14:51:23 +08:00
|
|
|
mark_initmem_nx();
|
2018-09-14 09:14:11 +08:00
|
|
|
init_mem_is_free = true;
|
2013-04-30 06:06:47 +08:00
|
|
|
free_initmem_default(POISON_FREE_INITMEM);
|
2011-06-18 15:36:39 +08:00
|
|
|
}
|
|
|
|
|
2019-11-04 10:32:56 +08:00
|
|
|
/**
|
|
|
|
* flush_coherent_icache() - if a CPU has a coherent icache, flush it
|
|
|
|
* @addr: The base address to use (can be any valid address, the whole cache will be flushed)
|
|
|
|
* Return true if the cache was flushed, false otherwise
|
|
|
|
*/
|
|
|
|
static inline bool flush_coherent_icache(unsigned long addr)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* For a snooping icache, we still need a dummy icbi to purge all the
|
|
|
|
* prefetched instructions from the ifetch buffers. We also need a sync
|
|
|
|
* before the icbi to order the the actual stores to memory that might
|
|
|
|
* have modified instructions with the icbi.
|
|
|
|
*/
|
|
|
|
if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
|
|
|
|
mb(); /* sync */
|
|
|
|
icbi((void *)addr);
|
|
|
|
mb(); /* sync */
|
|
|
|
isync();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* invalidate_icache_range() - Flush the icache by issuing icbi across an address range
|
|
|
|
* @start: the start address
|
|
|
|
* @stop: the stop address (exclusive)
|
|
|
|
*/
|
|
|
|
static void invalidate_icache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
|
|
|
unsigned long shift = l1_icache_shift();
|
|
|
|
unsigned long bytes = l1_icache_bytes();
|
|
|
|
char *addr = (char *)(start & ~(bytes - 1));
|
|
|
|
unsigned long size = stop - (unsigned long)addr + (bytes - 1);
|
|
|
|
unsigned long i;
|
|
|
|
|
|
|
|
for (i = 0; i < size >> shift; i++, addr += bytes)
|
|
|
|
icbi(addr);
|
|
|
|
|
|
|
|
mb(); /* sync */
|
|
|
|
isync();
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* flush_icache_range: Write any modified data cache blocks out to memory
|
|
|
|
* and invalidate the corresponding blocks in the instruction cache
|
|
|
|
*
|
|
|
|
* Generic code will call this after writing memory, before executing from it.
|
|
|
|
*
|
|
|
|
* @start: the start address
|
|
|
|
* @stop: the stop address (exclusive)
|
|
|
|
*/
|
|
|
|
void flush_icache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
|
|
|
if (flush_coherent_icache(start))
|
|
|
|
return;
|
|
|
|
|
|
|
|
clean_dcache_range(start, stop);
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_44x)) {
|
|
|
|
/*
|
|
|
|
* Flash invalidate on 44x because we are passed kmapped
|
|
|
|
* addresses and this doesn't work for userspace pages due to
|
|
|
|
* the virtually tagged icache.
|
|
|
|
*/
|
|
|
|
iccci((void *)start);
|
|
|
|
mb(); /* sync */
|
|
|
|
isync();
|
|
|
|
} else
|
|
|
|
invalidate_icache_range(start, stop);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_icache_range);
|
|
|
|
|
|
|
|
#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
|
|
|
|
/**
|
|
|
|
* flush_dcache_icache_phys() - Flush a page by it's physical address
|
|
|
|
* @physaddr: the physical address of the page
|
|
|
|
*/
|
|
|
|
static void flush_dcache_icache_phys(unsigned long physaddr)
|
|
|
|
{
|
|
|
|
unsigned long bytes = l1_dcache_bytes();
|
|
|
|
unsigned long nb = PAGE_SIZE / bytes;
|
|
|
|
unsigned long addr = physaddr & PAGE_MASK;
|
|
|
|
unsigned long msr, msr0;
|
|
|
|
unsigned long loop1 = addr, loop2 = addr;
|
|
|
|
|
|
|
|
msr0 = mfmsr();
|
|
|
|
msr = msr0 & ~MSR_DR;
|
|
|
|
/*
|
|
|
|
* This must remain as ASM to prevent potential memory accesses
|
|
|
|
* while the data MMU is disabled
|
|
|
|
*/
|
|
|
|
asm volatile(
|
|
|
|
" mtctr %2;\n"
|
|
|
|
" mtmsr %3;\n"
|
|
|
|
" isync;\n"
|
|
|
|
"0: dcbst 0, %0;\n"
|
|
|
|
" addi %0, %0, %4;\n"
|
|
|
|
" bdnz 0b;\n"
|
|
|
|
" sync;\n"
|
|
|
|
" mtctr %2;\n"
|
|
|
|
"1: icbi 0, %1;\n"
|
|
|
|
" addi %1, %1, %4;\n"
|
|
|
|
" bdnz 1b;\n"
|
|
|
|
" sync;\n"
|
|
|
|
" mtmsr %5;\n"
|
|
|
|
" isync;\n"
|
|
|
|
: "+&r" (loop1), "+&r" (loop2)
|
|
|
|
: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
|
|
|
|
: "ctr", "memory");
|
|
|
|
}
|
|
|
|
#endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
/*
|
|
|
|
* This is called when a page has been modified by the kernel.
|
|
|
|
* It just marks the page as not i-cache clean. We do the i-cache
|
|
|
|
* flush later when the page is given to a user process, if necessary.
|
|
|
|
*/
|
|
|
|
void flush_dcache_page(struct page *page)
|
|
|
|
{
|
|
|
|
if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
|
|
|
|
return;
|
|
|
|
/* avoid an atomic op if possible */
|
|
|
|
if (test_bit(PG_arch_1, &page->flags))
|
|
|
|
clear_bit(PG_arch_1, &page->flags);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_dcache_page);
|
|
|
|
|
|
|
|
void flush_dcache_icache_page(struct page *page)
|
|
|
|
{
|
2009-10-27 03:24:31 +08:00
|
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
|
|
if (PageCompound(page)) {
|
|
|
|
flush_dcache_icache_hugepage(page);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
2017-08-08 19:58:54 +08:00
|
|
|
#if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
|
2015-04-16 08:40:23 +08:00
|
|
|
/* On 8xx there is no need to kmap since highmem is not supported */
|
|
|
|
__flush_dcache_icache(page_address(page));
|
|
|
|
#else
|
|
|
|
if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
|
2011-11-25 23:14:16 +08:00
|
|
|
void *start = kmap_atomic(page);
|
2009-10-27 03:24:31 +08:00
|
|
|
__flush_dcache_icache(start);
|
2011-11-25 23:14:16 +08:00
|
|
|
kunmap_atomic(start);
|
2015-04-16 08:40:23 +08:00
|
|
|
} else {
|
2019-11-04 10:32:56 +08:00
|
|
|
unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
|
|
|
|
|
|
|
|
if (flush_coherent_icache(addr))
|
|
|
|
return;
|
|
|
|
flush_dcache_icache_phys(addr);
|
2009-10-27 03:24:31 +08:00
|
|
|
}
|
2005-09-26 14:04:21 +08:00
|
|
|
#endif
|
|
|
|
}
|
2012-08-03 19:56:33 +08:00
|
|
|
EXPORT_SYMBOL(flush_dcache_icache_page);
|
2009-10-27 03:24:31 +08:00
|
|
|
|
2019-11-04 10:32:56 +08:00
|
|
|
/**
|
|
|
|
* __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
|
|
|
|
* Note: this is necessary because the instruction cache does *not*
|
|
|
|
* snoop from the data cache.
|
|
|
|
*
|
|
|
|
* @page: the address of the page to flush
|
|
|
|
*/
|
|
|
|
void __flush_dcache_icache(void *p)
|
|
|
|
{
|
|
|
|
unsigned long addr = (unsigned long)p;
|
|
|
|
|
|
|
|
if (flush_coherent_icache(addr))
|
|
|
|
return;
|
|
|
|
|
|
|
|
clean_dcache_range(addr, addr + PAGE_SIZE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't flush the icache on 44x. Those have a virtual icache and we
|
|
|
|
* don't have access to the virtual address here (it's not the page
|
|
|
|
* vaddr but where it's mapped in user space). The flushing of the
|
|
|
|
* icache on these is handled elsewhere, when a change in the address
|
|
|
|
* space occurs, before returning to user space.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (cpu_has_feature(MMU_FTR_TYPE_44x))
|
|
|
|
return;
|
|
|
|
|
|
|
|
invalidate_icache_range(addr, addr + PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
2005-09-26 14:04:21 +08:00
|
|
|
void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
|
|
|
|
{
|
|
|
|
clear_page(page);
|
|
|
|
|
|
|
|
/*
|
2011-03-31 09:57:33 +08:00
|
|
|
* We shouldn't have to do this, but some versions of glibc
|
2005-09-26 14:04:21 +08:00
|
|
|
* require it (ld.so assumes zero filled pages are icache clean)
|
|
|
|
* - Anton
|
|
|
|
*/
|
2006-02-06 10:24:53 +08:00
|
|
|
flush_dcache_page(pg);
|
2005-09-26 14:04:21 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(clear_user_page);
|
|
|
|
|
|
|
|
void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
|
|
|
struct page *pg)
|
|
|
|
{
|
|
|
|
copy_page(vto, vfrom);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We should be able to use the following optimisation, however
|
|
|
|
* there are two problems.
|
|
|
|
* Firstly a bug in some versions of binutils meant PLT sections
|
|
|
|
* were not marked executable.
|
|
|
|
* Secondly the first word in the GOT section is blrl, used
|
|
|
|
* to establish the GOT address. Until recently the GOT was
|
|
|
|
* not marked executable.
|
|
|
|
* - Anton
|
|
|
|
*/
|
|
|
|
#if 0
|
|
|
|
if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
|
|
|
|
return;
|
|
|
|
#endif
|
|
|
|
|
2006-02-06 10:24:53 +08:00
|
|
|
flush_dcache_page(pg);
|
2005-09-26 14:04:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
|
|
|
|
unsigned long addr, int len)
|
|
|
|
{
|
|
|
|
unsigned long maddr;
|
|
|
|
|
|
|
|
maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
|
|
|
|
flush_icache_range(maddr, maddr + len);
|
|
|
|
kunmap(page);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_icache_user_range);
|
|
|
|
|
2011-11-02 22:56:12 +08:00
|
|
|
/*
|
|
|
|
* System memory should not be in /proc/iomem but various tools expect it
|
|
|
|
* (eg kdump).
|
|
|
|
*/
|
2013-09-15 17:39:36 +08:00
|
|
|
static int __init add_system_ram_resources(void)
|
2011-11-02 22:56:12 +08:00
|
|
|
{
|
|
|
|
struct memblock_region *reg;
|
|
|
|
|
|
|
|
for_each_memblock(memory, reg) {
|
|
|
|
struct resource *res;
|
|
|
|
unsigned long base = reg->base;
|
|
|
|
unsigned long size = reg->size;
|
|
|
|
|
|
|
|
res = kzalloc(sizeof(struct resource), GFP_KERNEL);
|
|
|
|
WARN_ON(!res);
|
|
|
|
|
|
|
|
if (res) {
|
|
|
|
res->name = "System RAM";
|
|
|
|
res->start = base;
|
|
|
|
res->end = base + size - 1;
|
2016-01-27 04:57:22 +08:00
|
|
|
res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
|
2011-11-02 22:56:12 +08:00
|
|
|
WARN_ON(request_resource(&iomem_resource, res) < 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
subsys_initcall(add_system_ram_resources);
|
2011-08-30 17:19:17 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_STRICT_DEVMEM
|
|
|
|
/*
|
|
|
|
* devmem_is_allowed(): check to see if /dev/mem access to a certain address
|
|
|
|
* is valid. The argument is a physical page number.
|
|
|
|
*
|
|
|
|
* Access has to be given to non-kernel-ram areas as well, these contain the
|
|
|
|
* PCI mmio resources as well as potential bios/acpi data regions.
|
|
|
|
*/
|
|
|
|
int devmem_is_allowed(unsigned long pfn)
|
|
|
|
{
|
2016-01-22 00:15:31 +08:00
|
|
|
if (page_is_rtas_user_buf(pfn))
|
|
|
|
return 1;
|
2015-04-18 05:17:14 +08:00
|
|
|
if (iomem_is_exclusive(PFN_PHYS(pfn)))
|
2011-08-30 17:19:17 +08:00
|
|
|
return 0;
|
|
|
|
if (!page_is_ram(pfn))
|
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_STRICT_DEVMEM */
|
2019-02-01 18:46:52 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This is defined in kernel/resource.c but only powerpc needs to export it, for
|
|
|
|
* the EHEA driver. Drop this when drivers/net/ethernet/ibm/ehea is removed.
|
|
|
|
*/
|
|
|
|
EXPORT_SYMBOL_GPL(walk_system_ram_range);
|