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linux/arch/mips/loongson64/cpucfg-emul.c

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MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
// SPDX-License-Identifier: GPL-2.0
#include <linux/smp.h>
#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <loongson_regs.h>
#include <cpucfg-emul.h>
static bool is_loongson(struct cpuinfo_mips *c)
{
switch (c->processor_id & PRID_COMP_MASK) {
case PRID_COMP_LEGACY:
return ((c->processor_id & PRID_IMP_MASK) ==
PRID_IMP_LOONGSON_64C);
case PRID_COMP_LOONGSON:
return true;
default:
return false;
}
}
static u32 get_loongson_fprev(struct cpuinfo_mips *c)
{
return c->fpu_id & LOONGSON_FPREV_MASK;
}
static bool cpu_has_uca(void)
{
u32 diag = read_c0_diag();
u32 new_diag;
if (diag & LOONGSON_DIAG_UCAC)
/* UCA is already enabled. */
return true;
/* See if UCAC bit can be flipped on. This should be safe. */
new_diag = diag | LOONGSON_DIAG_UCAC;
write_c0_diag(new_diag);
new_diag = read_c0_diag();
write_c0_diag(diag);
return (new_diag & LOONGSON_DIAG_UCAC) != 0;
}
static void probe_uca(struct cpuinfo_mips *c)
{
if (cpu_has_uca())
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LSUCA;
}
static void decode_loongson_config6(struct cpuinfo_mips *c)
{
u32 config6 = read_c0_config6();
if (config6 & MIPS_CONF6_LOONGSON_SFBEN)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
if (config6 & MIPS_CONF6_LOONGSON_LLEXC)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
if (config6 & MIPS_CONF6_LOONGSON_SCRAND)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
}
static void patch_cpucfg_sel1(struct cpuinfo_mips *c)
{
u64 ases = c->ases;
u64 options = c->options;
u32 data = c->loongson3_cpucfg_data[0];
if (options & MIPS_CPU_FPU) {
data |= LOONGSON_CFG1_FP;
data |= get_loongson_fprev(c) << LOONGSON_CFG1_FPREV_OFFSET;
}
if (ases & MIPS_ASE_LOONGSON_MMI)
data |= LOONGSON_CFG1_MMI;
if (ases & MIPS_ASE_MSA)
data |= LOONGSON_CFG1_MSA1;
c->loongson3_cpucfg_data[0] = data;
}
static void patch_cpucfg_sel2(struct cpuinfo_mips *c)
{
u64 ases = c->ases;
u64 options = c->options;
u32 data = c->loongson3_cpucfg_data[1];
if (ases & MIPS_ASE_LOONGSON_EXT)
data |= LOONGSON_CFG2_LEXT1;
if (ases & MIPS_ASE_LOONGSON_EXT2)
data |= LOONGSON_CFG2_LEXT2;
if (options & MIPS_CPU_LDPTE)
data |= LOONGSON_CFG2_LSPW;
if (ases & MIPS_ASE_VZ)
data |= LOONGSON_CFG2_LVZP;
else
data &= ~LOONGSON_CFG2_LVZREV;
c->loongson3_cpucfg_data[1] = data;
}
static void patch_cpucfg_sel3(struct cpuinfo_mips *c)
{
u64 ases = c->ases;
u32 data = c->loongson3_cpucfg_data[2];
if (ases & MIPS_ASE_LOONGSON_CAM) {
data |= LOONGSON_CFG3_LCAMP;
} else {
data &= ~LOONGSON_CFG3_LCAMREV;
data &= ~LOONGSON_CFG3_LCAMNUM;
data &= ~LOONGSON_CFG3_LCAMKW;
data &= ~LOONGSON_CFG3_LCAMVW;
}
c->loongson3_cpucfg_data[2] = data;
}
void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
{
/* Only engage the logic on Loongson processors. */
if (!is_loongson(c))
return;
/* CPUs with CPUCFG support don't need to synthesize anything. */
if (cpu_has_cfg())
return;
c->loongson3_cpucfg_data[0] = 0;
c->loongson3_cpucfg_data[1] = 0;
c->loongson3_cpucfg_data[2] = 0;
MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 15:32:41 +08:00
/* Add CPUCFG features non-discoverable otherwise. */
switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
c->loongson3_cpucfg_data[2] |= (
LOONGSON_CFG3_LCAM_REV1 |
LOONGSON_CFG3_LCAMNUM_REV1 |
LOONGSON_CFG3_LCAMKW_REV1 |
LOONGSON_CFG3_LCAMVW_REV1);
break;
MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 15:32:41 +08:00
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R2:
MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1);
c->loongson3_cpucfg_data[2] |= (
LOONGSON_CFG3_LCAM_REV1 |
LOONGSON_CFG3_LCAMNUM_REV1 |
LOONGSON_CFG3_LCAMKW_REV1 |
LOONGSON_CFG3_LCAMVW_REV1);
break;
MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 15:32:41 +08:00
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
decode_loongson_config6(c);
probe_uca(c);
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
LOONGSON_CFG2_LPM_REV2);
c->loongson3_cpucfg_data[2] = 0;
break;
MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 15:32:41 +08:00
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_1:
MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
decode_loongson_config6(c);
probe_uca(c);
c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_CNT64 |
LOONGSON_CFG1_LSLDR0 | LOONGSON_CFG1_LSPREF |
LOONGSON_CFG1_LSPREFX | LOONGSON_CFG1_LSSYNCI |
LOONGSON_CFG1_LLSYNC | LOONGSON_CFG1_TGTSYNC);
c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LBTMMU |
LOONGSON_CFG2_LPMP | LOONGSON_CFG2_LPM_REV1 |
LOONGSON_CFG2_LVZ_REV1);
c->loongson3_cpucfg_data[2] |= (LOONGSON_CFG3_LCAM_REV1 |
LOONGSON_CFG3_LCAMNUM_REV1 |
LOONGSON_CFG3_LCAMKW_REV1 |
LOONGSON_CFG3_LCAMVW_REV1);
break;
MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-30 15:32:41 +08:00
default:
/* It is possible that some future Loongson cores still do
* not have CPUCFG, so do not emulate anything for these
* cores.
*/
return;
MIPS: emulate CPUCFG instruction on older Loongson64 cores CPUCFG is the instruction for querying processor characteristics on newer Loongson processors, much like CPUID of x86. Since the instruction is supposedly designed to provide a unified way to do feature detection (without having to, for example, parse /proc/cpuinfo which is too heavyweight), it is important to provide compatibility for older cores without native support. Fortunately, most of the fields can be synthesized without changes to semantics. Performance is not really big a concern, because feature detection logic is not expected to be invoked very often in typical userland applications. The instruction can't be emulated on LOONGSON_2EF cores, according to FlyGoat's experiments. Because the LWC2 opcode is assigned to other valid instructions on 2E and 2F, no RI exception is raised for us to intercept. So compatibility is only extended back furthest to Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix of various blocks from the 3A/3B models from a kernel perspective. This is lightly based on Loongson's work on their Linux 3.10 fork, for being the authority on the right feature flags to fill in, where things aren't otherwise discoverable. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-23 21:37:01 +08:00
}
/* This feature is set by firmware, but all known Loongson-64 systems
* are configured this way.
*/
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_CDMAP;
/* Patch in dynamically probed bits. */
patch_cpucfg_sel1(c);
patch_cpucfg_sel2(c);
patch_cpucfg_sel3(c);
}