mirror of https://gitee.com/openkylin/linux.git
929 lines
20 KiB
ArmAsm
929 lines
20 KiB
ArmAsm
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//
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// assembly portion of the IA64 MCA handling
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//
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// Mods by cfleck to integrate into kernel build
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// 00/03/15 davidm Added various stop bits to get a clean compile
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//
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// 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
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// kstack, switch modes, jump to C INIT handler
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//
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// 02/01/04 J.Hall <jenna.s.hall@intel.com>
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// Before entering virtual mode code:
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// 1. Check for TLB CPU error
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// 2. Restore current thread pointer to kr6
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// 3. Move stack ptr 16 bytes to conform to C calling convention
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//
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// 04/11/12 Russ Anderson <rja@sgi.com>
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// Added per cpu MCA/INIT stack save areas.
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//
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <asm/asmmacro.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/mca_asm.h>
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#include <asm/mca.h>
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/*
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* When we get a machine check, the kernel stack pointer is no longer
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* valid, so we need to set a new stack pointer.
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*/
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#define MINSTATE_PHYS /* Make sure stack access is physical for MINSTATE */
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/*
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* Needed for return context to SAL
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*/
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#define IA64_MCA_SAME_CONTEXT 0
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#define IA64_MCA_COLD_BOOT -2
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#include "minstate.h"
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/*
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* SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
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* 1. GR1 = OS GP
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* 2. GR8 = PAL_PROC physical address
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* 3. GR9 = SAL_PROC physical address
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* 4. GR10 = SAL GP (physical)
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* 5. GR11 = Rendez state
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* 6. GR12 = Return address to location within SAL_CHECK
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*/
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#define SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(_tmp) \
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LOAD_PHYSICAL(p0, _tmp, ia64_sal_to_os_handoff_state);; \
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st8 [_tmp]=r1,0x08;; \
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st8 [_tmp]=r8,0x08;; \
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st8 [_tmp]=r9,0x08;; \
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st8 [_tmp]=r10,0x08;; \
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st8 [_tmp]=r11,0x08;; \
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st8 [_tmp]=r12,0x08;; \
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st8 [_tmp]=r17,0x08;; \
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st8 [_tmp]=r18,0x08
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/*
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* OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
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* (p6) is executed if we never entered virtual mode (TLB error)
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* (p7) is executed if we entered virtual mode as expected (normal case)
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* 1. GR8 = OS_MCA return status
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* 2. GR9 = SAL GP (physical)
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* 3. GR10 = 0/1 returning same/new context
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* 4. GR22 = New min state save area pointer
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* returns ptr to SAL rtn save loc in _tmp
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*/
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#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp) \
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movl _tmp=ia64_os_to_sal_handoff_state;; \
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DATA_VA_TO_PA(_tmp);; \
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ld8 r8=[_tmp],0x08;; \
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ld8 r9=[_tmp],0x08;; \
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ld8 r10=[_tmp],0x08;; \
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ld8 r22=[_tmp],0x08;;
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// now _tmp is pointing to SAL rtn save location
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/*
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* COLD_BOOT_HANDOFF_STATE() sets ia64_mca_os_to_sal_state
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* imots_os_status=IA64_MCA_COLD_BOOT
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* imots_sal_gp=SAL GP
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* imots_context=IA64_MCA_SAME_CONTEXT
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* imots_new_min_state=Min state save area pointer
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* imots_sal_check_ra=Return address to location within SAL_CHECK
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*
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*/
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#define COLD_BOOT_HANDOFF_STATE(sal_to_os_handoff,os_to_sal_handoff,tmp)\
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movl tmp=IA64_MCA_COLD_BOOT; \
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movl sal_to_os_handoff=__pa(ia64_sal_to_os_handoff_state); \
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movl os_to_sal_handoff=__pa(ia64_os_to_sal_handoff_state);; \
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st8 [os_to_sal_handoff]=tmp,8;; \
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ld8 tmp=[sal_to_os_handoff],48;; \
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st8 [os_to_sal_handoff]=tmp,8;; \
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movl tmp=IA64_MCA_SAME_CONTEXT;; \
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st8 [os_to_sal_handoff]=tmp,8;; \
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ld8 tmp=[sal_to_os_handoff],-8;; \
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st8 [os_to_sal_handoff]=tmp,8;; \
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ld8 tmp=[sal_to_os_handoff];; \
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st8 [os_to_sal_handoff]=tmp;;
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#define GET_IA64_MCA_DATA(reg) \
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GET_THIS_PADDR(reg, ia64_mca_data) \
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;; \
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ld8 reg=[reg]
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.global ia64_os_mca_dispatch
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.global ia64_os_mca_dispatch_end
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.global ia64_sal_to_os_handoff_state
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.global ia64_os_to_sal_handoff_state
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.text
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.align 16
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ia64_os_mca_dispatch:
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// Serialize all MCA processing
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mov r3=1;;
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LOAD_PHYSICAL(p0,r2,ia64_mca_serialize);;
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ia64_os_mca_spin:
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xchg8 r4=[r2],r3;;
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cmp.ne p6,p0=r4,r0
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(p6) br ia64_os_mca_spin
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// Save the SAL to OS MCA handoff state as defined
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// by SAL SPEC 3.0
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// NOTE : The order in which the state gets saved
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// is dependent on the way the C-structure
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// for ia64_mca_sal_to_os_state_t has been
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// defined in include/asm/mca.h
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SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
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;;
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// LOG PROCESSOR STATE INFO FROM HERE ON..
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begin_os_mca_dump:
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br ia64_os_mca_proc_state_dump;;
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ia64_os_mca_done_dump:
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LOAD_PHYSICAL(p0,r16,ia64_sal_to_os_handoff_state+56)
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;;
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ld8 r18=[r16] // Get processor state parameter on existing PALE_CHECK.
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;;
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tbit.nz p6,p7=r18,60
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(p7) br.spnt done_tlb_purge_and_reload
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// The following code purges TC and TR entries. Then reload all TC entries.
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// Purge percpu data TC entries.
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begin_tlb_purge_and_reload:
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#define O(member) IA64_CPUINFO_##member##_OFFSET
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GET_THIS_PADDR(r2, cpu_info) // load phys addr of cpu_info into r2
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;;
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addl r17=O(PTCE_STRIDE),r2
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addl r2=O(PTCE_BASE),r2
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;;
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ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
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ld4 r19=[r2],4 // r19=ptce_count[0]
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ld4 r21=[r17],4 // r21=ptce_stride[0]
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;;
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ld4 r20=[r2] // r20=ptce_count[1]
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ld4 r22=[r17] // r22=ptce_stride[1]
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mov r24=0
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;;
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adds r20=-1,r20
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;;
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#undef O
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2:
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cmp.ltu p6,p7=r24,r19
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(p7) br.cond.dpnt.few 4f
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mov ar.lc=r20
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3:
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ptc.e r18
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;;
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add r18=r22,r18
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br.cloop.sptk.few 3b
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;;
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add r18=r21,r18
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add r24=1,r24
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;;
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br.sptk.few 2b
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4:
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srlz.i // srlz.i implies srlz.d
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;;
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// Now purge addresses formerly mapped by TR registers
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// 1. Purge ITR&DTR for kernel.
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movl r16=KERNEL_START
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mov r18=KERNEL_TR_PAGE_SHIFT<<2
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;;
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ptr.i r16, r18
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ptr.d r16, r18
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;;
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srlz.i
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;;
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srlz.d
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;;
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// 2. Purge DTR for PERCPU data.
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movl r16=PERCPU_ADDR
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mov r18=PERCPU_PAGE_SHIFT<<2
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;;
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ptr.d r16,r18
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;;
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srlz.d
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;;
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// 3. Purge ITR for PAL code.
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GET_THIS_PADDR(r2, ia64_mca_pal_base)
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;;
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ld8 r16=[r2]
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mov r18=IA64_GRANULE_SHIFT<<2
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;;
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ptr.i r16,r18
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;;
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srlz.i
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;;
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// 4. Purge DTR for stack.
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mov r16=IA64_KR(CURRENT_STACK)
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;;
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shl r16=r16,IA64_GRANULE_SHIFT
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movl r19=PAGE_OFFSET
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;;
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add r16=r19,r16
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mov r18=IA64_GRANULE_SHIFT<<2
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;;
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ptr.d r16,r18
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;;
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srlz.i
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;;
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// Finally reload the TR registers.
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// 1. Reload DTR/ITR registers for kernel.
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mov r18=KERNEL_TR_PAGE_SHIFT<<2
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movl r17=KERNEL_START
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;;
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mov cr.itir=r18
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mov cr.ifa=r17
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mov r16=IA64_TR_KERNEL
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mov r19=ip
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movl r18=PAGE_KERNEL
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;;
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dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
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;;
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or r18=r17,r18
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;;
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itr.i itr[r16]=r18
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;;
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itr.d dtr[r16]=r18
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;;
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srlz.i
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srlz.d
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;;
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// 2. Reload DTR register for PERCPU data.
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GET_THIS_PADDR(r2, ia64_mca_per_cpu_pte)
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;;
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movl r16=PERCPU_ADDR // vaddr
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movl r18=PERCPU_PAGE_SHIFT<<2
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;;
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mov cr.itir=r18
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mov cr.ifa=r16
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;;
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ld8 r18=[r2] // load per-CPU PTE
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mov r16=IA64_TR_PERCPU_DATA;
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;;
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itr.d dtr[r16]=r18
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;;
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srlz.d
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;;
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// 3. Reload ITR for PAL code.
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GET_THIS_PADDR(r2, ia64_mca_pal_pte)
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;;
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ld8 r18=[r2] // load PAL PTE
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;;
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GET_THIS_PADDR(r2, ia64_mca_pal_base)
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;;
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ld8 r16=[r2] // load PAL vaddr
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mov r19=IA64_GRANULE_SHIFT<<2
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;;
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mov cr.itir=r19
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mov cr.ifa=r16
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mov r20=IA64_TR_PALCODE
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;;
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itr.i itr[r20]=r18
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;;
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srlz.i
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;;
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// 4. Reload DTR for stack.
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mov r16=IA64_KR(CURRENT_STACK)
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;;
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shl r16=r16,IA64_GRANULE_SHIFT
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movl r19=PAGE_OFFSET
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;;
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add r18=r19,r16
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movl r20=PAGE_KERNEL
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;;
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add r16=r20,r16
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mov r19=IA64_GRANULE_SHIFT<<2
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;;
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mov cr.itir=r19
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mov cr.ifa=r18
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mov r20=IA64_TR_CURRENT_STACK
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;;
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itr.d dtr[r20]=r16
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;;
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srlz.d
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;;
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br.sptk.many done_tlb_purge_and_reload
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err:
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COLD_BOOT_HANDOFF_STATE(r20,r21,r22)
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br.sptk.many ia64_os_mca_done_restore
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done_tlb_purge_and_reload:
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// Setup new stack frame for OS_MCA handling
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GET_IA64_MCA_DATA(r2)
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;;
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add r3 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
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add r2 = IA64_MCA_CPU_RBSTORE_OFFSET, r2
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;;
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rse_switch_context(r6,r3,r2);; // RSC management in this new context
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GET_IA64_MCA_DATA(r2)
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;;
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add r2 = IA64_MCA_CPU_STACK_OFFSET+IA64_MCA_STACK_SIZE-16, r2
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;;
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mov r12=r2 // establish new stack-pointer
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// Enter virtual mode from physical mode
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||
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VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
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ia64_os_mca_virtual_begin:
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// Call virtual mode handler
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||
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movl r2=ia64_mca_ucmc_handler;;
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mov b6=r2;;
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br.call.sptk.many b0=b6;;
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.ret0:
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// Revert back to physical mode before going back to SAL
|
||
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PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
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||
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ia64_os_mca_virtual_end:
|
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// restore the original stack frame here
|
||
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GET_IA64_MCA_DATA(r2)
|
||
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;;
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||
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add r2 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
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||
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;;
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||
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movl r4=IA64_PSR_MC
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||
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;;
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||
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rse_return_context(r4,r3,r2) // switch from interrupt context for RSE
|
||
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||
|
|
// let us restore all the registers from our PSI structure
|
||
|
|
mov r8=gp
|
||
|
|
;;
|
||
|
|
begin_os_mca_restore:
|
||
|
|
br ia64_os_mca_proc_state_restore;;
|
||
|
|
|
||
|
|
ia64_os_mca_done_restore:
|
||
|
|
OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2);;
|
||
|
|
// branch back to SALE_CHECK
|
||
|
|
ld8 r3=[r2];;
|
||
|
|
mov b0=r3;; // SAL_CHECK return address
|
||
|
|
|
||
|
|
// release lock
|
||
|
|
movl r3=ia64_mca_serialize;;
|
||
|
|
DATA_VA_TO_PA(r3);;
|
||
|
|
st8.rel [r3]=r0
|
||
|
|
|
||
|
|
br b0
|
||
|
|
;;
|
||
|
|
ia64_os_mca_dispatch_end:
|
||
|
|
//EndMain//////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
|
||
|
|
//++
|
||
|
|
// Name:
|
||
|
|
// ia64_os_mca_proc_state_dump()
|
||
|
|
//
|
||
|
|
// Stub Description:
|
||
|
|
//
|
||
|
|
// This stub dumps the processor state during MCHK to a data area
|
||
|
|
//
|
||
|
|
//--
|
||
|
|
|
||
|
|
ia64_os_mca_proc_state_dump:
|
||
|
|
// Save bank 1 GRs 16-31 which will be used by c-language code when we switch
|
||
|
|
// to virtual addressing mode.
|
||
|
|
GET_IA64_MCA_DATA(r2)
|
||
|
|
;;
|
||
|
|
add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
|
||
|
|
;;
|
||
|
|
// save ar.NaT
|
||
|
|
mov r5=ar.unat // ar.unat
|
||
|
|
|
||
|
|
// save banked GRs 16-31 along with NaT bits
|
||
|
|
bsw.1;;
|
||
|
|
st8.spill [r2]=r16,8;;
|
||
|
|
st8.spill [r2]=r17,8;;
|
||
|
|
st8.spill [r2]=r18,8;;
|
||
|
|
st8.spill [r2]=r19,8;;
|
||
|
|
st8.spill [r2]=r20,8;;
|
||
|
|
st8.spill [r2]=r21,8;;
|
||
|
|
st8.spill [r2]=r22,8;;
|
||
|
|
st8.spill [r2]=r23,8;;
|
||
|
|
st8.spill [r2]=r24,8;;
|
||
|
|
st8.spill [r2]=r25,8;;
|
||
|
|
st8.spill [r2]=r26,8;;
|
||
|
|
st8.spill [r2]=r27,8;;
|
||
|
|
st8.spill [r2]=r28,8;;
|
||
|
|
st8.spill [r2]=r29,8;;
|
||
|
|
st8.spill [r2]=r30,8;;
|
||
|
|
st8.spill [r2]=r31,8;;
|
||
|
|
|
||
|
|
mov r4=ar.unat;;
|
||
|
|
st8 [r2]=r4,8 // save User NaT bits for r16-r31
|
||
|
|
mov ar.unat=r5 // restore original unat
|
||
|
|
bsw.0;;
|
||
|
|
|
||
|
|
//save BRs
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2 // duplicate r2 in r4
|
||
|
|
|
||
|
|
mov r3=b0
|
||
|
|
mov r5=b1
|
||
|
|
mov r7=b2;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=b3
|
||
|
|
mov r5=b4
|
||
|
|
mov r7=b5;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=b6
|
||
|
|
mov r5=b7;;
|
||
|
|
st8 [r2]=r3,2*8
|
||
|
|
st8 [r4]=r5,2*8;;
|
||
|
|
|
||
|
|
cSaveCRs:
|
||
|
|
// save CRs
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2 // duplicate r2 in r4
|
||
|
|
|
||
|
|
mov r3=cr.dcr
|
||
|
|
mov r5=cr.itm
|
||
|
|
mov r7=cr.iva;;
|
||
|
|
|
||
|
|
st8 [r2]=r3,8*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;; // 48 byte rements
|
||
|
|
|
||
|
|
mov r3=cr.pta;;
|
||
|
|
st8 [r2]=r3,8*8;; // 64 byte rements
|
||
|
|
|
||
|
|
// if PSR.ic=0, reading interruption registers causes an illegal operation fault
|
||
|
|
mov r3=psr;;
|
||
|
|
tbit.nz.unc p6,p0=r3,PSR_IC;; // PSI Valid Log bit pos. test
|
||
|
|
(p6) st8 [r2]=r0,9*8+160 // increment by 232 byte inc.
|
||
|
|
begin_skip_intr_regs:
|
||
|
|
(p6) br SkipIntrRegs;;
|
||
|
|
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2 // duplicate r2 in r6
|
||
|
|
|
||
|
|
mov r3=cr.ipsr
|
||
|
|
mov r5=cr.isr
|
||
|
|
mov r7=r0;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=cr.iip
|
||
|
|
mov r5=cr.ifa
|
||
|
|
mov r7=cr.itir;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=cr.iipa
|
||
|
|
mov r5=cr.ifs
|
||
|
|
mov r7=cr.iim;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=cr25;; // cr.iha
|
||
|
|
st8 [r2]=r3,160;; // 160 byte rement
|
||
|
|
|
||
|
|
SkipIntrRegs:
|
||
|
|
st8 [r2]=r0,152;; // another 152 byte .
|
||
|
|
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2 // duplicate r2 in r6
|
||
|
|
|
||
|
|
mov r3=cr.lid
|
||
|
|
// mov r5=cr.ivr // cr.ivr, don't read it
|
||
|
|
mov r7=cr.tpr;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=r0 // cr.eoi => cr67
|
||
|
|
mov r5=r0 // cr.irr0 => cr68
|
||
|
|
mov r7=r0;; // cr.irr1 => cr69
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=r0 // cr.irr2 => cr70
|
||
|
|
mov r5=r0 // cr.irr3 => cr71
|
||
|
|
mov r7=cr.itv;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=cr.pmv
|
||
|
|
mov r5=cr.cmcv;;
|
||
|
|
st8 [r2]=r3,7*8
|
||
|
|
st8 [r4]=r5,7*8;;
|
||
|
|
|
||
|
|
mov r3=r0 // cr.lrr0 => cr80
|
||
|
|
mov r5=r0;; // cr.lrr1 => cr81
|
||
|
|
st8 [r2]=r3,23*8
|
||
|
|
st8 [r4]=r5,23*8;;
|
||
|
|
|
||
|
|
adds r2=25*8,r2;;
|
||
|
|
|
||
|
|
cSaveARs:
|
||
|
|
// save ARs
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2 // duplicate r2 in r6
|
||
|
|
|
||
|
|
mov r3=ar.k0
|
||
|
|
mov r5=ar.k1
|
||
|
|
mov r7=ar.k2;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=ar.k3
|
||
|
|
mov r5=ar.k4
|
||
|
|
mov r7=ar.k5;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=ar.k6
|
||
|
|
mov r5=ar.k7
|
||
|
|
mov r7=r0;; // ar.kr8
|
||
|
|
st8 [r2]=r3,10*8
|
||
|
|
st8 [r4]=r5,10*8
|
||
|
|
st8 [r6]=r7,10*8;; // rement by 72 bytes
|
||
|
|
|
||
|
|
mov r3=ar.rsc
|
||
|
|
mov ar.rsc=r0 // put RSE in enforced lazy mode
|
||
|
|
mov r5=ar.bsp
|
||
|
|
;;
|
||
|
|
mov r7=ar.bspstore;;
|
||
|
|
st8 [r2]=r3,3*8
|
||
|
|
st8 [r4]=r5,3*8
|
||
|
|
st8 [r6]=r7,3*8;;
|
||
|
|
|
||
|
|
mov r3=ar.rnat;;
|
||
|
|
st8 [r2]=r3,8*13 // increment by 13x8 bytes
|
||
|
|
|
||
|
|
mov r3=ar.ccv;;
|
||
|
|
st8 [r2]=r3,8*4
|
||
|
|
|
||
|
|
mov r3=ar.unat;;
|
||
|
|
st8 [r2]=r3,8*4
|
||
|
|
|
||
|
|
mov r3=ar.fpsr;;
|
||
|
|
st8 [r2]=r3,8*4
|
||
|
|
|
||
|
|
mov r3=ar.itc;;
|
||
|
|
st8 [r2]=r3,160 // 160
|
||
|
|
|
||
|
|
mov r3=ar.pfs;;
|
||
|
|
st8 [r2]=r3,8
|
||
|
|
|
||
|
|
mov r3=ar.lc;;
|
||
|
|
st8 [r2]=r3,8
|
||
|
|
|
||
|
|
mov r3=ar.ec;;
|
||
|
|
st8 [r2]=r3
|
||
|
|
add r2=8*62,r2 //padding
|
||
|
|
|
||
|
|
// save RRs
|
||
|
|
mov ar.lc=0x08-1
|
||
|
|
movl r4=0x00;;
|
||
|
|
|
||
|
|
cStRR:
|
||
|
|
dep.z r5=r4,61,3;;
|
||
|
|
mov r3=rr[r5];;
|
||
|
|
st8 [r2]=r3,8
|
||
|
|
add r4=1,r4
|
||
|
|
br.cloop.sptk.few cStRR
|
||
|
|
;;
|
||
|
|
end_os_mca_dump:
|
||
|
|
br ia64_os_mca_done_dump;;
|
||
|
|
|
||
|
|
//EndStub//////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
|
||
|
|
//++
|
||
|
|
// Name:
|
||
|
|
// ia64_os_mca_proc_state_restore()
|
||
|
|
//
|
||
|
|
// Stub Description:
|
||
|
|
//
|
||
|
|
// This is a stub to restore the saved processor state during MCHK
|
||
|
|
//
|
||
|
|
//--
|
||
|
|
|
||
|
|
ia64_os_mca_proc_state_restore:
|
||
|
|
|
||
|
|
// Restore bank1 GR16-31
|
||
|
|
GET_IA64_MCA_DATA(r2)
|
||
|
|
;;
|
||
|
|
add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
|
||
|
|
|
||
|
|
restore_GRs: // restore bank-1 GRs 16-31
|
||
|
|
bsw.1;;
|
||
|
|
add r3=16*8,r2;; // to get to NaT of GR 16-31
|
||
|
|
ld8 r3=[r3];;
|
||
|
|
mov ar.unat=r3;; // first restore NaT
|
||
|
|
|
||
|
|
ld8.fill r16=[r2],8;;
|
||
|
|
ld8.fill r17=[r2],8;;
|
||
|
|
ld8.fill r18=[r2],8;;
|
||
|
|
ld8.fill r19=[r2],8;;
|
||
|
|
ld8.fill r20=[r2],8;;
|
||
|
|
ld8.fill r21=[r2],8;;
|
||
|
|
ld8.fill r22=[r2],8;;
|
||
|
|
ld8.fill r23=[r2],8;;
|
||
|
|
ld8.fill r24=[r2],8;;
|
||
|
|
ld8.fill r25=[r2],8;;
|
||
|
|
ld8.fill r26=[r2],8;;
|
||
|
|
ld8.fill r27=[r2],8;;
|
||
|
|
ld8.fill r28=[r2],8;;
|
||
|
|
ld8.fill r29=[r2],8;;
|
||
|
|
ld8.fill r30=[r2],8;;
|
||
|
|
ld8.fill r31=[r2],8;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],8;; // increment to skip NaT
|
||
|
|
bsw.0;;
|
||
|
|
|
||
|
|
restore_BRs:
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2;; // duplicate r2 in r4
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov b0=r3
|
||
|
|
mov b1=r5
|
||
|
|
mov b2=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov b3=r3
|
||
|
|
mov b4=r5
|
||
|
|
mov b5=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],2*8
|
||
|
|
ld8 r5=[r4],2*8;;
|
||
|
|
mov b6=r3
|
||
|
|
mov b7=r5;;
|
||
|
|
|
||
|
|
restore_CRs:
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2;; // duplicate r2 in r4
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;; // 48 byte increments
|
||
|
|
mov cr.dcr=r3
|
||
|
|
mov cr.itm=r5
|
||
|
|
mov cr.iva=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*8;; // 64 byte increments
|
||
|
|
// mov cr.pta=r3
|
||
|
|
|
||
|
|
|
||
|
|
// if PSR.ic=1, reading interruption registers causes an illegal operation fault
|
||
|
|
mov r3=psr;;
|
||
|
|
tbit.nz.unc p6,p0=r3,PSR_IC;; // PSI Valid Log bit pos. test
|
||
|
|
(p6) st8 [r2]=r0,9*8+160 // increment by 232 byte inc.
|
||
|
|
|
||
|
|
begin_rskip_intr_regs:
|
||
|
|
(p6) br rSkipIntrRegs;;
|
||
|
|
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2;; // duplicate r2 in r4
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov cr.ipsr=r3
|
||
|
|
// mov cr.isr=r5 // cr.isr is read only
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov cr.iip=r3
|
||
|
|
mov cr.ifa=r5
|
||
|
|
mov cr.itir=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov cr.iipa=r3
|
||
|
|
mov cr.ifs=r5
|
||
|
|
mov cr.iim=r7
|
||
|
|
|
||
|
|
ld8 r3=[r2],160;; // 160 byte increment
|
||
|
|
mov cr.iha=r3
|
||
|
|
|
||
|
|
rSkipIntrRegs:
|
||
|
|
ld8 r3=[r2],152;; // another 152 byte inc.
|
||
|
|
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2;; // duplicate r2 in r6
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*3
|
||
|
|
ld8 r5=[r4],8*3
|
||
|
|
ld8 r7=[r6],8*3;;
|
||
|
|
mov cr.lid=r3
|
||
|
|
// mov cr.ivr=r5 // cr.ivr is read only
|
||
|
|
mov cr.tpr=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*3
|
||
|
|
ld8 r5=[r4],8*3
|
||
|
|
ld8 r7=[r6],8*3;;
|
||
|
|
// mov cr.eoi=r3
|
||
|
|
// mov cr.irr0=r5 // cr.irr0 is read only
|
||
|
|
// mov cr.irr1=r7;; // cr.irr1 is read only
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*3
|
||
|
|
ld8 r5=[r4],8*3
|
||
|
|
ld8 r7=[r6],8*3;;
|
||
|
|
// mov cr.irr2=r3 // cr.irr2 is read only
|
||
|
|
// mov cr.irr3=r5 // cr.irr3 is read only
|
||
|
|
mov cr.itv=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*7
|
||
|
|
ld8 r5=[r4],8*7;;
|
||
|
|
mov cr.pmv=r3
|
||
|
|
mov cr.cmcv=r5;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*23
|
||
|
|
ld8 r5=[r4],8*23;;
|
||
|
|
adds r2=8*23,r2
|
||
|
|
adds r4=8*23,r4;;
|
||
|
|
// mov cr.lrr0=r3
|
||
|
|
// mov cr.lrr1=r5
|
||
|
|
|
||
|
|
adds r2=8*2,r2;;
|
||
|
|
|
||
|
|
restore_ARs:
|
||
|
|
add r4=8,r2 // duplicate r2 in r4
|
||
|
|
add r6=2*8,r2;; // duplicate r2 in r4
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov ar.k0=r3
|
||
|
|
mov ar.k1=r5
|
||
|
|
mov ar.k2=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
mov ar.k3=r3
|
||
|
|
mov ar.k4=r5
|
||
|
|
mov ar.k5=r7;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],10*8
|
||
|
|
ld8 r5=[r4],10*8
|
||
|
|
ld8 r7=[r6],10*8;;
|
||
|
|
mov ar.k6=r3
|
||
|
|
mov ar.k7=r5
|
||
|
|
;;
|
||
|
|
|
||
|
|
ld8 r3=[r2],3*8
|
||
|
|
ld8 r5=[r4],3*8
|
||
|
|
ld8 r7=[r6],3*8;;
|
||
|
|
// mov ar.rsc=r3
|
||
|
|
// mov ar.bsp=r5 // ar.bsp is read only
|
||
|
|
mov ar.rsc=r0 // make sure that RSE is in enforced lazy mode
|
||
|
|
;;
|
||
|
|
mov ar.bspstore=r7;;
|
||
|
|
|
||
|
|
ld8 r9=[r2],8*13;;
|
||
|
|
mov ar.rnat=r9
|
||
|
|
|
||
|
|
mov ar.rsc=r3
|
||
|
|
ld8 r3=[r2],8*4;;
|
||
|
|
mov ar.ccv=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*4;;
|
||
|
|
mov ar.unat=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2],8*4;;
|
||
|
|
mov ar.fpsr=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2],160;; // 160
|
||
|
|
// mov ar.itc=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2],8;;
|
||
|
|
mov ar.pfs=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2],8;;
|
||
|
|
mov ar.lc=r3
|
||
|
|
|
||
|
|
ld8 r3=[r2];;
|
||
|
|
mov ar.ec=r3
|
||
|
|
add r2=8*62,r2;; // padding
|
||
|
|
|
||
|
|
restore_RRs:
|
||
|
|
mov r5=ar.lc
|
||
|
|
mov ar.lc=0x08-1
|
||
|
|
movl r4=0x00;;
|
||
|
|
cStRRr:
|
||
|
|
dep.z r7=r4,61,3
|
||
|
|
ld8 r3=[r2],8;;
|
||
|
|
mov rr[r7]=r3 // what are its access previledges?
|
||
|
|
add r4=1,r4
|
||
|
|
br.cloop.sptk.few cStRRr
|
||
|
|
;;
|
||
|
|
mov ar.lc=r5
|
||
|
|
;;
|
||
|
|
end_os_mca_restore:
|
||
|
|
br ia64_os_mca_done_restore;;
|
||
|
|
|
||
|
|
//EndStub//////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
|
||
|
|
// ok, the issue here is that we need to save state information so
|
||
|
|
// it can be useable by the kernel debugger and show regs routines.
|
||
|
|
// In order to do this, our best bet is save the current state (plus
|
||
|
|
// the state information obtain from the MIN_STATE_AREA) into a pt_regs
|
||
|
|
// format. This way we can pass it on in a useable format.
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// SAL to OS entry point for INIT on the monarch processor
|
||
|
|
// This has been defined for registration purposes with SAL
|
||
|
|
// as a part of ia64_mca_init.
|
||
|
|
//
|
||
|
|
// When we get here, the following registers have been
|
||
|
|
// set by the SAL for our use
|
||
|
|
//
|
||
|
|
// 1. GR1 = OS INIT GP
|
||
|
|
// 2. GR8 = PAL_PROC physical address
|
||
|
|
// 3. GR9 = SAL_PROC physical address
|
||
|
|
// 4. GR10 = SAL GP (physical)
|
||
|
|
// 5. GR11 = Init Reason
|
||
|
|
// 0 = Received INIT for event other than crash dump switch
|
||
|
|
// 1 = Received wakeup at the end of an OS_MCA corrected machine check
|
||
|
|
// 2 = Received INIT dude to CrashDump switch assertion
|
||
|
|
//
|
||
|
|
// 6. GR12 = Return address to location within SAL_INIT procedure
|
||
|
|
|
||
|
|
|
||
|
|
GLOBAL_ENTRY(ia64_monarch_init_handler)
|
||
|
|
.prologue
|
||
|
|
// stash the information the SAL passed to os
|
||
|
|
SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
|
||
|
|
;;
|
||
|
|
SAVE_MIN_WITH_COVER
|
||
|
|
;;
|
||
|
|
mov r8=cr.ifa
|
||
|
|
mov r9=cr.isr
|
||
|
|
adds r3=8,r2 // set up second base pointer
|
||
|
|
;;
|
||
|
|
SAVE_REST
|
||
|
|
|
||
|
|
// ok, enough should be saved at this point to be dangerous, and supply
|
||
|
|
// information for a dump
|
||
|
|
// We need to switch to Virtual mode before hitting the C functions.
|
||
|
|
|
||
|
|
movl r2=IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN
|
||
|
|
mov r3=psr // get the current psr, minimum enabled at this point
|
||
|
|
;;
|
||
|
|
or r2=r2,r3
|
||
|
|
;;
|
||
|
|
movl r3=IVirtual_Switch
|
||
|
|
;;
|
||
|
|
mov cr.iip=r3 // short return to set the appropriate bits
|
||
|
|
mov cr.ipsr=r2 // need to do an rfi to set appropriate bits
|
||
|
|
;;
|
||
|
|
rfi
|
||
|
|
;;
|
||
|
|
IVirtual_Switch:
|
||
|
|
//
|
||
|
|
// We should now be running virtual
|
||
|
|
//
|
||
|
|
// Let's call the C handler to get the rest of the state info
|
||
|
|
//
|
||
|
|
alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
|
||
|
|
;;
|
||
|
|
adds out0=16,sp // out0 = pointer to pt_regs
|
||
|
|
;;
|
||
|
|
DO_SAVE_SWITCH_STACK
|
||
|
|
.body
|
||
|
|
adds out1=16,sp // out0 = pointer to switch_stack
|
||
|
|
|
||
|
|
br.call.sptk.many rp=ia64_init_handler
|
||
|
|
.ret1:
|
||
|
|
|
||
|
|
return_from_init:
|
||
|
|
br.sptk return_from_init
|
||
|
|
END(ia64_monarch_init_handler)
|
||
|
|
|
||
|
|
//
|
||
|
|
// SAL to OS entry point for INIT on the slave processor
|
||
|
|
// This has been defined for registration purposes with SAL
|
||
|
|
// as a part of ia64_mca_init.
|
||
|
|
//
|
||
|
|
|
||
|
|
GLOBAL_ENTRY(ia64_slave_init_handler)
|
||
|
|
1: br.sptk 1b
|
||
|
|
END(ia64_slave_init_handler)
|