mirror of https://gitee.com/openkylin/linux.git
469 lines
12 KiB
C
469 lines
12 KiB
C
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/* $Id$
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2001 by Hiroyuki Kondo
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*/
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#ifndef __ASSEMBLY__
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typedef void V;
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typedef char B;
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typedef short S;
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typedef int W;
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typedef long L;
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typedef float F;
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typedef double D;
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typedef unsigned char UB;
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typedef unsigned short US;
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typedef unsigned int UW;
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typedef unsigned long UL;
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typedef const unsigned int CUW;
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/*********************************
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M32102 ICU
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*********************************/
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#define ICUISTS (UW *)0xa0EFF004
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#define ICUIREQ0 (UW *)0xa0EFF008
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#define ICUIREQ1 (UW *)0xa0EFF00C
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#define ICUSBICR (UW *)0xa0EFF018
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#define ICUIMASK (UW *)0xa0EFF01C
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#define ICUCR1 (UW *)0xa0EFF200 /* INT0 */
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#define ICUCR2 (UW *)0xa0EFF204 /* INT1 */
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#define ICUCR3 (UW *)0xa0EFF208 /* INT2 */
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#define ICUCR4 (UW *)0xa0EFF20C /* INT3 */
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#define ICUCR5 (UW *)0xa0EFF210 /* INT4 */
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#define ICUCR6 (UW *)0xa0EFF214 /* INT5 */
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#define ICUCR7 (UW *)0xa0EFF218 /* INT6 */
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#define ICUCR16 (UW *)0xa0EFF23C /* MFT0 */
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#define ICUCR17 (UW *)0xa0EFF240 /* MFT1 */
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#define ICUCR18 (UW *)0xa0EFF244 /* MFT2 */
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#define ICUCR19 (UW *)0xa0EFF248 /* MFT3 */
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#define ICUCR20 (UW *)0xa0EFF24C /* MFT4 */
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#define ICUCR21 (UW *)0xa0EFF250 /* MFT5 */
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#define ICUCR32 (UW *)0xa0EFF27C /* DMA0 */
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#define ICUCR33 (UW *)0xa0EFF280 /* DMA1 */
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#define ICUCR48 (UW *)0xa0EFF2BC /* SIO0R */
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#define ICUCR49 (UW *)0xa0EFF2C0 /* SIO0S */
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#define ICUCR50 (UW *)0xa0EFF2C4 /* SIO1R */
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#define ICUCR51 (UW *)0xa0EFF2C8 /* SIO1S */
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#define ICUCR52 (UW *)0xa0EFF2CC /* SIO2R */
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#define ICUCR53 (UW *)0xa0EFF2D0 /* SIO2S */
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#define ICUCR54 (UW *)0xa0EFF2D4 /* SIO3R */
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#define ICUCR55 (UW *)0xa0EFF2D8 /* SIO3S */
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#define ICUCR56 (UW *)0xa0EFF2DC /* SIO4R */
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#define ICUCR57 (UW *)0xa0EFF2E0 /* SIO4S */
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/*********************************
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M32102 MFT
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*********************************/
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#define MFTCR (US *)0xa0EFC002
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#define MFTRPR (UB *)0xa0EFC006
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#define MFT0MOD (US *)0xa0EFC102
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#define MFT0BOS (US *)0xa0EFC106
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#define MFT0CUT (US *)0xa0EFC10A
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#define MFT0RLD (US *)0xa0EFC10E
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#define MFT0CRLD (US *)0xa0EFC112
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#define MFT1MOD (US *)0xa0EFC202
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#define MFT1BOS (US *)0xa0EFC206
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#define MFT1CUT (US *)0xa0EFC20A
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#define MFT1RLD (US *)0xa0EFC20E
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#define MFT1CRLD (US *)0xa0EFC212
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#define MFT2MOD (US *)0xa0EFC302
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#define MFT2BOS (US *)0xa0EFC306
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#define MFT2CUT (US *)0xa0EFC30A
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#define MFT2RLD (US *)0xa0EFC30E
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#define MFT2CRLD (US *)0xa0EFC312
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#define MFT3MOD (US *)0xa0EFC402
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#define MFT3CUT (US *)0xa0EFC40A
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#define MFT3RLD (US *)0xa0EFC40E
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#define MFT3CRLD (US *)0xa0EFC412
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#define MFT4MOD (US *)0xa0EFC502
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#define MFT4CUT (US *)0xa0EFC50A
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#define MFT4RLD (US *)0xa0EFC50E
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#define MFT4CRLD (US *)0xa0EFC512
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#define MFT5MOD (US *)0xa0EFC602
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#define MFT5CUT (US *)0xa0EFC60A
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#define MFT5RLD (US *)0xa0EFC60E
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#define MFT5CRLD (US *)0xa0EFC612
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/*********************************
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M32102 SIO
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*********************************/
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#define SIO0CR (volatile int *)0xa0efd000
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#define SIO0MOD0 (volatile int *)0xa0efd004
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#define SIO0MOD1 (volatile int *)0xa0efd008
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#define SIO0STS (volatile int *)0xa0efd00c
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#define SIO0IMASK (volatile int *)0xa0efd010
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#define SIO0BAUR (volatile int *)0xa0efd014
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#define SIO0RBAUR (volatile int *)0xa0efd018
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#define SIO0TXB (volatile int *)0xa0efd01c
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#define SIO0RXB (volatile int *)0xa0efd020
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#define SIO1CR (volatile int *)0xa0efd100
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#define SIO1MOD0 (volatile int *)0xa0efd104
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#define SIO1MOD1 (volatile int *)0xa0efd108
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#define SIO1STS (volatile int *)0xa0efd10c
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#define SIO1IMASK (volatile int *)0xa0efd110
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#define SIO1BAUR (volatile int *)0xa0efd114
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#define SIO1RBAUR (volatile int *)0xa0efd118
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#define SIO1TXB (volatile int *)0xa0efd11c
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#define SIO1RXB (volatile int *)0xa0efd120
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/*********************************
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M32102 PORT
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*********************************/
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#define PIEN (UB *)0xa0EF1003 /* input enable */
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#define P0DATA (UB *)0xa0EF1020 /* data */
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#define P1DATA (UB *)0xa0EF1021
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#define P2DATA (UB *)0xa0EF1022
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#define P3DATA (UB *)0xa0EF1023
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#define P4DATA (UB *)0xa0EF1024
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#define P5DATA (UB *)0xa0EF1025
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#define P6DATA (UB *)0xa0EF1026
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#define P7DATA (UB *)0xa0EF1027
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#define P0DIR (UB *)0xa0EF1040 /* direction */
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#define P1DIR (UB *)0xa0EF1041
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#define P2DIR (UB *)0xa0EF1042
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#define P3DIR (UB *)0xa0EF1043
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#define P4DIR (UB *)0xa0EF1044
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#define P5DIR (UB *)0xa0EF1045
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#define P6DIR (UB *)0xa0EF1046
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#define P7DIR (UB *)0xa0EF1047
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#define P0MOD (US *)0xa0EF1060 /* mode control */
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#define P1MOD (US *)0xa0EF1062
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#define P2MOD (US *)0xa0EF1064
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#define P3MOD (US *)0xa0EF1066
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#define P4MOD (US *)0xa0EF1068
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#define P5MOD (US *)0xa0EF106A
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#define P6MOD (US *)0xa0EF106C
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#define P7MOD (US *)0xa0EF106E
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#define P0ODCR (UB *)0xa0EF1080 /* open-drain control */
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#define P1ODCR (UB *)0xa0EF1081
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#define P2ODCR (UB *)0xa0EF1082
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#define P3ODCR (UB *)0xa0EF1083
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#define P4ODCR (UB *)0xa0EF1084
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#define P5ODCR (UB *)0xa0EF1085
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#define P6ODCR (UB *)0xa0EF1086
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#define P7ODCR (UB *)0xa0EF1087
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/*********************************
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M32102 Cache
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********************************/
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#define MCCR (US *)0xFFFFFFFE
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#else /* __ASSEMBLY__ */
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;;
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;; PIO 0x80ef1000
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;;
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#define PIEN 0xa0ef1000
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#define P0DATA 0xa0ef1020
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#define P1DATA 0xa0ef1021
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#define P2DATA 0xa0ef1022
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#define P3DATA 0xa0ef1023
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#define P4DATA 0xa0ef1024
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#define P5DATA 0xa0ef1025
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#define P6DATA 0xa0ef1026
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#define P7DATA 0xa0ef1027
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#define P0DIR 0xa0ef1040
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#define P1DIR 0xa0ef1041
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#define P2DIR 0xa0ef1042
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#define P3DIR 0xa0ef1043
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#define P4DIR 0xa0ef1044
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#define P5DIR 0xa0ef1045
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#define P6DIR 0xa0ef1046
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#define P7DIR 0xa0ef1047
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#define P0MOD 0xa0ef1060
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#define P1MOD 0xa0ef1062
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#define P2MOD 0xa0ef1064
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#define P3MOD 0xa0ef1066
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#define P4MOD 0xa0ef1068
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#define P5MOD 0xa0ef106a
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#define P6MOD 0xa0ef106c
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#define P7MOD 0xa0ef106e
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;
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#define P0ODCR 0xa0ef1080
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#define P1ODCR 0xa0ef1081
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#define P2ODCR 0xa0ef1082
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#define P3ODCR 0xa0ef1083
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#define P4ODCR 0xa0ef1084
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#define P5ODCR 0xa0ef1085
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#define P6ODCR 0xa0ef1086
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#define P7ODCR 0xa0ef1087
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;;
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;; WDT 0xa0ef2000
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;;
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#define WDTCR 0xa0ef2000
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;;
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;; CLK 0xa0ef4000
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;;
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#define CPUCLKCR 0xa0ef4000
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#define CLKMOD 0xa0ef4004
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#define PLLCR 0xa0ef4008
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;;
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;; BSEL 0xa0ef5000
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;;
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#define BSEL0CR 0xa0ef5000
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#define BSEL1CR 0xa0ef5004
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#define BSEL2CR 0xa0ef5008
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#define BSEL3CR 0xa0ef500c
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#define BSEL4CR 0xa0ef5010
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#define BSEL5CR 0xa0ef5014
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;;
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;; SDRAMC 0xa0ef6000
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;;
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#define SDRF0 0xa0ef6000
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#define SDRF1 0xa0ef6004
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#define SDIR0 0xa0ef6008
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#define SDIR1 0xa0ef600c
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#define SDBR 0xa0ef6010
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;; CH0
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#define SD0ADR 0xa0ef6020
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#define SD0SZ 0xa0ef6022
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#define SD0ER 0xa0ef6024
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#define SD0TR 0xa0ef6028
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#define SD0MOD 0xa0ef602c
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;; CH1
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#define SD1ADR 0xa0ef6040
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#define SD1SZ 0xa0ef6042
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#define SD1ER 0xa0ef6044
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#define SD1TR 0xa0ef6048
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#define SD1MOD 0xa0ef604c
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;;
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;; DMAC 0xa0ef8000
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;;
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#define DMAEN 0xa0ef8000
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#define DMAISTS 0xa0ef8004
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#define DMAEDET 0xa0ef8008
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#define DMAASTS 0xa0ef800c
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;; CH0
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#define DMA0CR0 0xa0ef8100
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#define DMA0CR1 0xa0ef8104
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#define DMA0CSA 0xa0ef8108
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#define DMA0RSA 0xa0ef810c
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#define DMA0CDA 0xa0ef8110
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#define DMA0RDA 0xa0ef8114
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#define DMA0CBCUT 0xa0ef8118
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#define DMA0RBCUT 0xa0ef811c
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;; CH1
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#define DMA1CR0 0xa0ef8200
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#define DMA1CR1 0xa0ef8204
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#define DMA1CSA 0xa0ef8208
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#define DMA1RSA 0xa0ef820c
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#define DMA1CDA 0xa0ef8210
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#define DMA1RDA 0xa0ef8214
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#define DMA1CBCUT 0xa0ef8218
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#define DMA1RBCUT 0xa0ef821c
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;;
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;; MFT 0xa0efc000
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;;
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#define MFTCR 0xa0efc000
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#define MFTRPR 0xa0efc004
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;; CH0
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#define MFT0MOD 0xa0efc100
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#define MFT0BOS 0xa0efc104
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#define MFT0CUT 0xa0efc108
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#define MFT0RLD 0xa0efc10c
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#define MFT0CMPRLD 0xa0efc110
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;; CH1
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#define MFT1MOD 0xa0efc200
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#define MFT1BOS 0xa0efc204
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#define MFT1CUT 0xa0efc208
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#define MFT1RLD 0xa0efc20c
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#define MFT1CMPRLD 0xa0efc210
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;; CH2
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#define MFT2MOD 0xa0efc300
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#define MFT2BOS 0xa0efc304
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#define MFT2CUT 0xa0efc308
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#define MFT2RLD 0xa0efc30c
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#define MFT2CMPRLD 0xa0efc310
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;; CH3
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#define MFT3MOD 0xa0efc400
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#define MFT3BOS 0xa0efc404
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#define MFT3CUT 0xa0efc408
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#define MFT3RLD 0xa0efc40c
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#define MFT3CMPRLD 0xa0efc410
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;; CH4
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#define MFT4MOD 0xa0efc500
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#define MFT4BOS 0xa0efc504
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#define MFT4CUT 0xa0efc508
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#define MFT4RLD 0xa0efc50c
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#define MFT4CMPRLD 0xa0efc510
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||
|
|
;; CH5
|
||
|
|
#define MFT5MOD 0xa0efc600
|
||
|
|
#define MFT5BOS 0xa0efc604
|
||
|
|
#define MFT5CUT 0xa0efc608
|
||
|
|
#define MFT5RLD 0xa0efc60c
|
||
|
|
#define MFT5CMPRLD 0xa0efc610
|
||
|
|
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; SIO 0xa0efd000
|
||
|
|
;;
|
||
|
|
|
||
|
|
;; CH0
|
||
|
|
#define SIO0CR 0xa0efd000
|
||
|
|
#define SIO0MOD0 0xa0efd004
|
||
|
|
#define SIO0MOD1 0xa0efd008
|
||
|
|
#define SIO0STS 0xa0efd00c
|
||
|
|
#define SIO0IMASK 0xa0efd010
|
||
|
|
#define SIO0BAUR 0xa0efd014
|
||
|
|
#define SIO0RBAUR 0xa0efd018
|
||
|
|
#define SIO0TXB 0xa0efd01c
|
||
|
|
#define SIO0RXB 0xa0efd020
|
||
|
|
|
||
|
|
;; CH1
|
||
|
|
#define SIO1CR 0xa0efd100
|
||
|
|
#define SIO1MOD0 0xa0efd104
|
||
|
|
#define SIO1MOD1 0xa0efd108
|
||
|
|
#define SIO1STS 0xa0efd10c
|
||
|
|
#define SIO1IMASK 0xa0efd110
|
||
|
|
#define SIO1BAUR 0xa0efd114
|
||
|
|
#define SIO1RBAUR 0xa0efd118
|
||
|
|
#define SIO1TXB 0xa0efd11c
|
||
|
|
#define SIO1RXB 0xa0efd120
|
||
|
|
|
||
|
|
;; CH2
|
||
|
|
#define SIO2CR 0xa0efd200
|
||
|
|
#define SIO2MOD0 0xa0efd204
|
||
|
|
#define SIO2MOD1 0xa0efd208
|
||
|
|
#define SIO2STS 0xa0efd20c
|
||
|
|
#define SIO2IMASK 0xa0efd210
|
||
|
|
#define SIO2BAUR 0xa0efd214
|
||
|
|
#define SIO2RBAUR 0xa0efd218
|
||
|
|
#define SIO2TXB 0xa0efd21c
|
||
|
|
#define SIO2RXB 0xa0efd220
|
||
|
|
|
||
|
|
;; CH3
|
||
|
|
#define SIO3CR 0xa0efd300
|
||
|
|
#define SIO3MOD0 0xa0efd304
|
||
|
|
#define SIO3MOD1 0xa0efd308
|
||
|
|
#define SIO3STS 0xa0efd30c
|
||
|
|
#define SIO3IMASK 0xa0efd310
|
||
|
|
#define SIO3BAUR 0xa0efd314
|
||
|
|
#define SIO3RBAUR 0xa0efd318
|
||
|
|
#define SIO3TXB 0xa0efd31c
|
||
|
|
#define SIO3RXB 0xa0efd320
|
||
|
|
|
||
|
|
;; CH4
|
||
|
|
#define SIO4CR 0xa0efd400
|
||
|
|
#define SIO4MOD0 0xa0efd404
|
||
|
|
#define SIO4MOD1 0xa0efd408
|
||
|
|
#define SIO4STS 0xa0efd40c
|
||
|
|
#define SIO4IMASK 0xa0efd410
|
||
|
|
#define SIO4BAUR 0xa0efd414
|
||
|
|
#define SIO4RBAUR 0xa0efd418
|
||
|
|
#define SIO4TXB 0xa0efd41c
|
||
|
|
#define SIO4RXB 0xa0efd420
|
||
|
|
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; ICU 0xa0eff000
|
||
|
|
;;
|
||
|
|
|
||
|
|
#define ICUISTS 0xa0eff004
|
||
|
|
#define ICUIREQ0 0xa0eff008
|
||
|
|
#define ICUIREQ1 0xa0eff00c
|
||
|
|
|
||
|
|
#define ICUSBICR 0xa0eff018
|
||
|
|
#define ICUIMASK 0xa0eff01c
|
||
|
|
|
||
|
|
#define ICUCR1 0xa0eff200
|
||
|
|
#define ICUCR2 0xa0eff204
|
||
|
|
#define ICUCR3 0xa0eff208
|
||
|
|
#define ICUCR4 0xa0eff20c
|
||
|
|
#define ICUCR5 0xa0eff210
|
||
|
|
#define ICUCR6 0xa0eff214
|
||
|
|
#define ICUCR7 0xa0eff218
|
||
|
|
|
||
|
|
#define ICUCR16 0xa0eff23c
|
||
|
|
#define ICUCR17 0xa0eff240
|
||
|
|
#define ICUCR18 0xa0eff244
|
||
|
|
#define ICUCR19 0xa0eff248
|
||
|
|
#define ICUCR20 0xa0eff24c
|
||
|
|
#define ICUCR21 0xa0eff250
|
||
|
|
|
||
|
|
#define ICUCR32 0xa0eff27c
|
||
|
|
#define ICUCR33 0xa0eff280
|
||
|
|
|
||
|
|
#define ICUCR48 0xa0eff2bc
|
||
|
|
#define ICUCR49 0xa0eff2c0
|
||
|
|
#define ICUCR50 0xa0eff2c4
|
||
|
|
#define ICUCR51 0xa0eff2c8
|
||
|
|
#define ICUCR52 0xa0eff2cc
|
||
|
|
#define ICUCR53 0xa0eff2d0
|
||
|
|
#define ICUCR54 0xa0eff2d4
|
||
|
|
#define ICUCR55 0xa0eff2d8
|
||
|
|
#define ICUCR56 0xa0eff2dc
|
||
|
|
#define ICUCR57 0xa0eff2e0
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; CACHE
|
||
|
|
;;
|
||
|
|
|
||
|
|
#define MCCR 0xfffffffc
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* __ASSEMBLY__ */
|