2013-03-22 22:34:09 +08:00
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/*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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2014-02-11 20:40:52 +08:00
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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2013-03-22 22:34:09 +08:00
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*
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2014-02-11 20:40:52 +08:00
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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2013-03-22 22:34:09 +08:00
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*
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2014-02-11 20:40:52 +08:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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2013-03-22 22:34:09 +08:00
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*/
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#ifndef _UAPI_TEGRA_DRM_H_
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#define _UAPI_TEGRA_DRM_H_
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2013-04-27 01:49:51 +08:00
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#include <drm/drm.h>
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2013-10-07 15:47:58 +08:00
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
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2013-10-05 04:34:01 +08:00
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2013-03-22 22:34:09 +08:00
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struct drm_tegra_gem_create {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_tegra_gem_mmap {
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__u32 handle;
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__u32 offset;
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};
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struct drm_tegra_syncpt_read {
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__u32 id;
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__u32 value;
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};
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struct drm_tegra_syncpt_incr {
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__u32 id;
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__u32 pad;
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};
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struct drm_tegra_syncpt_wait {
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__u32 id;
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__u32 thresh;
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__u32 timeout;
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__u32 value;
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};
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#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
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struct drm_tegra_open_channel {
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__u32 client;
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__u32 pad;
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__u64 context;
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};
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struct drm_tegra_close_channel {
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__u64 context;
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};
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struct drm_tegra_get_syncpt {
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__u64 context;
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__u32 index;
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__u32 id;
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};
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2013-10-14 20:21:54 +08:00
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struct drm_tegra_get_syncpt_base {
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__u64 context;
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__u32 syncpt;
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__u32 id;
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};
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2013-03-22 22:34:09 +08:00
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struct drm_tegra_syncpt {
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__u32 id;
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__u32 incrs;
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};
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struct drm_tegra_cmdbuf {
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__u32 handle;
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__u32 offset;
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__u32 words;
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__u32 pad;
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};
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struct drm_tegra_reloc {
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struct {
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__u32 handle;
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__u32 offset;
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} cmdbuf;
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struct {
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__u32 handle;
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__u32 offset;
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} target;
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__u32 shift;
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__u32 pad;
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};
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struct drm_tegra_waitchk {
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__u32 handle;
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__u32 offset;
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__u32 syncpt;
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__u32 thresh;
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};
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struct drm_tegra_submit {
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__u64 context;
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__u32 num_syncpts;
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__u32 num_cmdbufs;
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__u32 num_relocs;
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__u32 num_waitchks;
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__u32 waitchk_mask;
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__u32 timeout;
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__u64 syncpts;
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__u64 cmdbufs;
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__u64 relocs;
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__u64 waitchks;
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__u32 fence; /* Return value */
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__u32 reserved[5]; /* future expansion */
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};
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2014-06-03 20:56:57 +08:00
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#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
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#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
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#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
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struct drm_tegra_gem_set_tiling {
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/* input */
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__u32 handle;
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__u32 mode;
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__u32 value;
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__u32 pad;
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};
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struct drm_tegra_gem_get_tiling {
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/* input */
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__u32 handle;
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/* output */
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__u32 mode;
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__u32 value;
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__u32 pad;
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};
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2013-10-14 20:21:54 +08:00
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#define DRM_TEGRA_GEM_CREATE 0x00
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#define DRM_TEGRA_GEM_MMAP 0x01
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#define DRM_TEGRA_SYNCPT_READ 0x02
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#define DRM_TEGRA_SYNCPT_INCR 0x03
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#define DRM_TEGRA_SYNCPT_WAIT 0x04
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#define DRM_TEGRA_OPEN_CHANNEL 0x05
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06
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#define DRM_TEGRA_GET_SYNCPT 0x07
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#define DRM_TEGRA_SUBMIT 0x08
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#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
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2014-06-03 20:56:57 +08:00
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#define DRM_TEGRA_GEM_SET_TILING 0x0a
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#define DRM_TEGRA_GEM_GET_TILING 0x0b
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2013-03-22 22:34:09 +08:00
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#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
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#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
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#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
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#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
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#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
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#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
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#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
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2013-10-14 20:21:54 +08:00
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#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
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2014-06-03 20:56:57 +08:00
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#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
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#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
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2013-03-22 22:34:09 +08:00
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#endif
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