2013-10-02 08:13:49 +08:00
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/*
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* Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
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*
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* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/watchdog.h>
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#include <linux/platform_device.h>
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#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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2013-11-12 04:33:44 +08:00
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#define CLOCK_FREQ 1000000
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2013-10-02 08:13:49 +08:00
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#define SIRFSOC_TIMER_COUNTER_LO 0x0000
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#define SIRFSOC_TIMER_MATCH_0 0x0008
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#define SIRFSOC_TIMER_INT_EN 0x0024
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#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
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#define SIRFSOC_TIMER_LATCH 0x0030
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#define SIRFSOC_TIMER_LATCHED_LO 0x0034
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#define SIRFSOC_TIMER_WDT_INDEX 5
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#define SIRFSOC_WDT_MIN_TIMEOUT 30 /* 30 secs */
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#define SIRFSOC_WDT_MAX_TIMEOUT (10 * 60) /* 10 mins */
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#define SIRFSOC_WDT_DEFAULT_TIMEOUT 30 /* 30 secs */
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static unsigned int timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT;
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(timeout, uint, 0);
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
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{
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u32 counter, match;
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void __iomem *wdt_base;
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int time_left;
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wdt_base = watchdog_get_drvdata(wdd);
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counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO);
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match = readl(wdt_base +
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SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
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time_left = match - counter;
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2013-11-12 04:33:44 +08:00
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return time_left / CLOCK_FREQ;
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2013-10-02 08:13:49 +08:00
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}
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static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
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{
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u32 counter, timeout_ticks;
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void __iomem *wdt_base;
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2013-11-12 04:33:44 +08:00
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timeout_ticks = wdd->timeout * CLOCK_FREQ;
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2013-10-02 08:13:49 +08:00
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wdt_base = watchdog_get_drvdata(wdd);
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/* Enable the latch before reading the LATCH_LO register */
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writel(1, wdt_base + SIRFSOC_TIMER_LATCH);
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/* Set the TO value */
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counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO);
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counter += timeout_ticks;
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writel(counter, wdt_base +
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SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
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return 0;
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}
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static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
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{
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void __iomem *wdt_base = watchdog_get_drvdata(wdd);
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sirfsoc_wdt_updatetimeout(wdd);
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/*
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* NOTE: If interrupt is not enabled
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* then WD-Reset doesn't get generated at all.
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*/
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writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
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| (1 << SIRFSOC_TIMER_WDT_INDEX),
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wdt_base + SIRFSOC_TIMER_INT_EN);
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writel(1, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
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return 0;
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}
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static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
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{
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void __iomem *wdt_base = watchdog_get_drvdata(wdd);
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writel(0, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
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writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
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& (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
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wdt_base + SIRFSOC_TIMER_INT_EN);
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return 0;
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}
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static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
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{
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wdd->timeout = to;
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sirfsoc_wdt_updatetimeout(wdd);
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return 0;
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}
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#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
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static const struct watchdog_info sirfsoc_wdt_ident = {
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.options = OPTIONS,
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.firmware_version = 0,
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.identity = "SiRFSOC Watchdog",
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};
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static struct watchdog_ops sirfsoc_wdt_ops = {
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.owner = THIS_MODULE,
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.start = sirfsoc_wdt_enable,
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.stop = sirfsoc_wdt_disable,
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.get_timeleft = sirfsoc_wdt_gettimeleft,
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.ping = sirfsoc_wdt_updatetimeout,
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.set_timeout = sirfsoc_wdt_settimeout,
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};
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static struct watchdog_device sirfsoc_wdd = {
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.info = &sirfsoc_wdt_ident,
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.ops = &sirfsoc_wdt_ops,
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.timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
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.min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
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.max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
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};
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static int sirfsoc_wdt_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret;
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void __iomem *base;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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watchdog_set_drvdata(&sirfsoc_wdd, base);
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watchdog_init_timeout(&sirfsoc_wdd, timeout, &pdev->dev);
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watchdog_set_nowayout(&sirfsoc_wdd, nowayout);
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ret = watchdog_register_device(&sirfsoc_wdd);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, &sirfsoc_wdd);
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return 0;
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}
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static void sirfsoc_wdt_shutdown(struct platform_device *pdev)
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{
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struct watchdog_device *wdd = platform_get_drvdata(pdev);
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sirfsoc_wdt_disable(wdd);
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}
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static int sirfsoc_wdt_remove(struct platform_device *pdev)
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{
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sirfsoc_wdt_shutdown(pdev);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int sirfsoc_wdt_suspend(struct device *dev)
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{
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return 0;
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}
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static int sirfsoc_wdt_resume(struct device *dev)
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{
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struct watchdog_device *wdd = dev_get_drvdata(dev);
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/*
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* NOTE: Since timer controller registers settings are saved
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* and restored back by the timer-prima2.c, so we need not
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* update WD settings except refreshing timeout.
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*/
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sirfsoc_wdt_updatetimeout(wdd);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(sirfsoc_wdt_pm_ops,
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sirfsoc_wdt_suspend, sirfsoc_wdt_resume);
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static const struct of_device_id sirfsoc_wdt_of_match[] = {
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{ .compatible = "sirf,prima2-tick"},
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{},
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};
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MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);
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static struct platform_driver sirfsoc_wdt_driver = {
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.driver = {
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.name = "sirfsoc-wdt",
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.owner = THIS_MODULE,
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.pm = &sirfsoc_wdt_pm_ops,
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.of_match_table = of_match_ptr(sirfsoc_wdt_of_match),
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},
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.probe = sirfsoc_wdt_probe,
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.remove = sirfsoc_wdt_remove,
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.shutdown = sirfsoc_wdt_shutdown,
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};
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module_platform_driver(sirfsoc_wdt_driver);
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MODULE_DESCRIPTION("SiRF SoC watchdog driver");
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MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:sirfsoc-wdt");
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