2018-07-17 23:42:56 +08:00
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* Amlogic Audio TDM formatters
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Required properties:
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- compatible: 'amlogic,axg-tdmin' or
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2019-04-04 19:17:28 +08:00
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'amlogic,axg-tdmout' or
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'amlogic,g12a-tdmin' or
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2019-09-05 20:01:13 +08:00
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'amlogic,g12a-tdmout' or
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'amlogic,sm1-tdmin' or
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'amlogic,sm1-tdmout
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2018-07-17 23:42:56 +08:00
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- reg: physical base address of the controller and length of memory
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mapped region.
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- clocks: list of clock phandle, one for each entry clock-names.
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- clock-names: should contain the following:
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* "pclk" : peripheral clock.
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* "sclk" : bit clock.
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* "sclk_sel" : bit clock input multiplexer.
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* "lrclk" : sample clock
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* "lrclk_sel": sample clock input multiplexer
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2019-07-03 20:07:48 +08:00
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Optional property:
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- resets: phandle to the dedicated reset line of the tdm formatter.
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Example of TDMOUT_A on the S905X2 SoC:
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2018-07-17 23:42:56 +08:00
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tdmout_a: audio-controller@500 {
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compatible = "amlogic,axg-tdmout";
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reg = <0x0 0x500 0x0 0x40>;
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2019-07-03 20:07:48 +08:00
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resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
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2018-07-17 23:42:56 +08:00
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clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
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<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
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clock-names = "pclk", "sclk", "sclk_sel",
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"lrclk", "lrclk_sel";
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};
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