2007-02-15 17:20:52 +08:00
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/*
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* arch/sh/kernel/io_generic.c
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2005-04-17 06:20:36 +08:00
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*
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* Copyright (C) 2000 Niibe Yutaka
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2007-02-15 17:20:52 +08:00
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* Copyright (C) 2005 - 2007 Paul Mundt
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2005-04-17 06:20:36 +08:00
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*
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* Generic I/O routine. These can be used where a machine specific version
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* is not required.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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2006-01-17 14:14:15 +08:00
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#include <linux/module.h>
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2007-02-15 17:20:52 +08:00
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#include <linux/io.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/machvec.h>
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2006-01-17 14:14:15 +08:00
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#ifdef CONFIG_CPU_SH3
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/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
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* workaround. */
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2005-04-17 06:20:36 +08:00
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/* I'm not sure SH7709 has this kind of bug */
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2006-01-17 14:14:15 +08:00
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#define dummy_read() ctrl_inb(0xba000000)
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#else
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#define dummy_read()
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2005-04-17 06:20:36 +08:00
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#endif
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unsigned long generic_io_base;
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static inline void delay(void)
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{
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ctrl_inw(0xa0000000);
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}
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2006-01-17 14:14:15 +08:00
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u8 generic_inb(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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return ctrl_inb((unsigned long __force)__ioport_map(port, 1));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u16 generic_inw(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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return ctrl_inw((unsigned long __force)__ioport_map(port, 2));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u32 generic_inl(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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return ctrl_inl((unsigned long __force)__ioport_map(port, 4));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u8 generic_inb_p(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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unsigned long v = generic_inb(port);
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2005-04-17 06:20:36 +08:00
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delay();
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return v;
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}
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2006-01-17 14:14:15 +08:00
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u16 generic_inw_p(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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unsigned long v = generic_inw(port);
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2005-04-17 06:20:36 +08:00
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delay();
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return v;
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}
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2006-01-17 14:14:15 +08:00
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u32 generic_inl_p(unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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unsigned long v = generic_inl(port);
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2005-04-17 06:20:36 +08:00
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delay();
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return v;
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}
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/*
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* insb/w/l all read a series of bytes/words/longs from a fixed port
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* address. However as the port address doesn't change we only need to
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* convert the port address to real address once.
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*/
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2006-01-17 14:14:15 +08:00
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void generic_insb(unsigned long port, void *dst, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u8 *port_addr;
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u8 *buf = dst;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u8 *)__ioport_map(port, 1);
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2006-01-17 14:14:15 +08:00
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while (count--)
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*buf++ = *port_addr;
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_insw(unsigned long port, void *dst, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u16 *port_addr;
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u16 *buf = dst;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u16 *)__ioport_map(port, 2);
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2006-01-17 14:14:15 +08:00
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while (count--)
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*buf++ = *port_addr;
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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dummy_read();
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_insl(unsigned long port, void *dst, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u32 *port_addr;
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u32 *buf = dst;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u32 *)__ioport_map(port, 4);
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2006-01-17 14:14:15 +08:00
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while (count--)
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*buf++ = *port_addr;
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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dummy_read();
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outb(u8 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outw(u16 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outl(u32 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2008-02-07 19:18:21 +08:00
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ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4));
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outb_p(u8 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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generic_outb(b, port);
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2005-04-17 06:20:36 +08:00
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delay();
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}
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2006-01-17 14:14:15 +08:00
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void generic_outw_p(u16 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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generic_outw(b, port);
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2005-04-17 06:20:36 +08:00
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delay();
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}
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2006-01-17 14:14:15 +08:00
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void generic_outl_p(u32 b, unsigned long port)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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generic_outl(b, port);
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2005-04-17 06:20:36 +08:00
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delay();
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}
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/*
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* outsb/w/l all write a series of bytes/words/longs to a fixed port
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* address. However as the port address doesn't change we only need to
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* convert the port address to real address once.
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*/
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2006-01-17 14:14:15 +08:00
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void generic_outsb(unsigned long port, const void *src, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u8 *port_addr;
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const u8 *buf = src;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u8 __force *)__ioport_map(port, 1);
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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while (count--)
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*port_addr = *buf++;
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outsw(unsigned long port, const void *src, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u16 *port_addr;
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const u16 *buf = src;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u16 __force *)__ioport_map(port, 2);
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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while (count--)
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*port_addr = *buf++;
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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dummy_read();
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_outsl(unsigned long port, const void *src, unsigned long count)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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volatile u32 *port_addr;
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const u32 *buf = src;
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2005-04-17 06:20:36 +08:00
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2008-02-07 19:18:21 +08:00
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port_addr = (volatile u32 __force *)__ioport_map(port, 4);
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2006-01-17 14:14:15 +08:00
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while (count--)
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*port_addr = *buf++;
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2005-04-17 06:20:36 +08:00
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2006-01-17 14:14:15 +08:00
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dummy_read();
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u8 generic_readb(void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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return ctrl_inb((unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u16 generic_readw(void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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return ctrl_inw((unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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u32 generic_readl(void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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return ctrl_inl((unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_writeb(u8 b, void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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ctrl_outb(b, (unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_writew(u16 b, void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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ctrl_outw(b, (unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_writel(u32 b, void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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ctrl_outl(b, (unsigned long __force)addr);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
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2005-04-17 06:20:36 +08:00
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{
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2006-01-17 14:14:15 +08:00
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return (void __iomem *)(addr + generic_io_base);
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2005-04-17 06:20:36 +08:00
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}
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2006-01-17 14:14:15 +08:00
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void generic_ioport_unmap(void __iomem *addr)
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2005-04-17 06:20:36 +08:00
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{
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}
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