2016-11-05 05:53:38 +08:00
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/*
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* Device Tree Source for the r8a7745 SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
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#include <dt-bindings/power/r8a7745-sysc.h>
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/ {
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compatible = "renesas,r8a7745";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
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power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
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next-level-cache = <&L2_CA7>;
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};
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2017-03-07 00:40:38 +08:00
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L2_CA7: cache-controller-0 {
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2016-11-05 05:53:38 +08:00
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7745_PD_CA7_SCU>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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2017-01-18 17:27:28 +08:00
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<0 0xf1002000 0 0x2000>,
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2016-11-05 05:53:38 +08:00
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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2017-01-17 20:49:18 +08:00
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 408>;
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2016-11-05 05:53:38 +08:00
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};
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2016-11-05 05:59:37 +08:00
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7745", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 407>;
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2016-11-05 05:59:37 +08:00
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};
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2016-11-05 05:53:38 +08:00
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7745-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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2017-03-16 22:07:26 +08:00
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#reset-cells = <1>;
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2016-11-05 05:53:38 +08:00
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};
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2016-11-18 18:37:43 +08:00
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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2016-11-18 18:24:23 +08:00
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7745-rst";
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reg = <0 0xe6160000 0 0x100>;
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};
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2016-11-05 05:53:38 +08:00
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7745-sysc";
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reg = <0 0xe6180000 0 0x200>;
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#power-domain-cells = <1>;
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};
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2016-11-05 05:54:51 +08:00
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7745",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 219>;
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2016-11-05 05:54:51 +08:00
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a7745",
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"renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 218>;
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2016-11-05 05:54:51 +08:00
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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2016-11-05 05:55:52 +08:00
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c40000 0 0x40>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>;
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clock-names = "fck";
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dmas = <&dmac0 0x21>, <&dmac0 0x22>,
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<&dmac1 0x21>, <&dmac1 0x22>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 204>;
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2016-11-05 05:55:52 +08:00
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c50000 0 0x40>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>;
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clock-names = "fck";
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dmas = <&dmac0 0x25>, <&dmac0 0x26>,
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<&dmac1 0x25>, <&dmac1 0x26>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 203>;
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2016-11-05 05:55:52 +08:00
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c60000 0 0x40>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 202>;
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clock-names = "fck";
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dmas = <&dmac0 0x27>, <&dmac0 0x28>,
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<&dmac1 0x27>, <&dmac1 0x28>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 202>;
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2016-11-05 05:55:52 +08:00
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c70000 0 0x40>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 1106>;
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clock-names = "fck";
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dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
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<&dmac1 0x1b>, <&dmac1 0x1c>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 1106>;
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2016-11-05 05:55:52 +08:00
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status = "disabled";
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};
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scifa4: serial@e6c78000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c78000 0 0x40>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 1107>;
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clock-names = "fck";
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dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
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<&dmac1 0x1f>, <&dmac1 0x20>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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2017-03-16 22:07:26 +08:00
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resets = <&cpg 1107>;
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2016-11-05 05:55:52 +08:00
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status = "disabled";
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};
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scifa5: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7745",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c80000 0 0x40>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 1108>;
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clock-names = "fck";
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dmas = <&dmac0 0x23>, <&dmac0 0x24>,
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|
|
|
|
<&dmac1 0x23>, <&dmac1 0x24>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 1108>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb0: serial@e6c20000 {
|
|
|
|
|
compatible = "renesas,scifb-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
|
|
|
reg = <0 0xe6c20000 0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 206>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
|
2017-02-09 02:00:44 +08:00
|
|
|
<&dmac1 0x3d>, <&dmac1 0x3e>;
|
2016-11-05 05:55:52 +08:00
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 206>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb1: serial@e6c30000 {
|
|
|
|
|
compatible = "renesas,scifb-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
|
|
|
reg = <0 0xe6c30000 0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 207>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
|
|
|
|
|
<&dmac1 0x19>, <&dmac1 0x1a>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 207>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb2: serial@e6ce0000 {
|
|
|
|
|
compatible = "renesas,scifb-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
|
|
|
reg = <0 0xe6ce0000 0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 216>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
|
|
|
|
|
<&dmac1 0x1d>, <&dmac1 0x1e>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 216>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif0: serial@e6e60000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6e60000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 721>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
|
|
|
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 721>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif1: serial@e6e68000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6e68000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 720>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
|
|
|
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 720>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif2: serial@e6e58000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6e58000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 719>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
|
|
|
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 719>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif3: serial@e6ea8000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6ea8000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 718>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
|
|
|
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 718>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif4: serial@e6ee0000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6ee0000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 715>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
|
|
|
|
|
<&dmac1 0xfb>, <&dmac1 0xfc>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 715>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif5: serial@e6ee8000 {
|
|
|
|
|
compatible = "renesas,scif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
|
|
|
reg = <0 0xe6ee8000 0 0x40>;
|
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 714>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
|
|
|
|
|
<&dmac1 0xfd>, <&dmac1 0xfe>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 714>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hscif0: serial@e62c0000 {
|
|
|
|
|
compatible = "renesas,hscif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
|
|
|
reg = <0 0xe62c0000 0 0x60>;
|
|
|
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 717>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
|
|
|
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 717>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hscif1: serial@e62c8000 {
|
|
|
|
|
compatible = "renesas,hscif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
|
|
|
reg = <0 0xe62c8000 0 0x60>;
|
|
|
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 716>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
|
|
|
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 716>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hscif2: serial@e62d0000 {
|
|
|
|
|
compatible = "renesas,hscif-r8a7745",
|
|
|
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
|
|
|
reg = <0 0xe62d0000 0 0x60>;
|
|
|
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 713>,
|
|
|
|
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
|
|
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
|
|
|
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
|
|
|
|
|
<&dmac1 0x3b>, <&dmac1 0x3c>;
|
|
|
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 713>;
|
2016-11-05 05:55:52 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2016-11-05 05:57:01 +08:00
|
|
|
|
|
|
|
|
ether: ethernet@ee700000 {
|
|
|
|
|
compatible = "renesas,ether-r8a7745";
|
|
|
|
|
reg = <0 0xee700000 0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&cpg CPG_MOD 813>;
|
|
|
|
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
2017-03-16 22:07:26 +08:00
|
|
|
resets = <&cpg 813>;
|
2016-11-05 05:57:01 +08:00
|
|
|
phy-mode = "rmii";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2016-11-05 05:53:38 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* External root clock */
|
|
|
|
|
extal_clk: extal {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
/* This value must be overridden by the board. */
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* External USB clock - can be overridden by the board */
|
|
|
|
|
usb_extal_clk: usb_extal {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* External SCIF clock */
|
|
|
|
|
scif_clk: scif {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
/* This value must be overridden by the board. */
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
