2005-04-17 06:20:36 +08:00
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/*
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* TLB support routines.
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*
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* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* 08/02/00 A. Mallick <asit.k.mallick@intel.com>
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* Modified RID allocation for SMP
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* Goutham Rao <goutham.rao@intel.com>
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* IPI based ptc implementation and A-step IPI implementation.
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2005-11-01 05:44:47 +08:00
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* Rohit Seth <rohit.seth@intel.com>
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* Ken Chen <kenneth.w.chen@intel.com>
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2007-12-13 23:03:07 +08:00
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* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
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2005-04-17 06:20:36 +08:00
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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2005-11-01 05:44:47 +08:00
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#include <linux/bootmem.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/delay.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#include <asm/pal.h>
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#include <asm/tlbflush.h>
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2005-11-01 05:44:47 +08:00
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#include <asm/dma.h>
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2005-04-17 06:20:36 +08:00
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static struct {
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unsigned long mask; /* mask of supported purge page-sizes */
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2005-10-30 09:47:04 +08:00
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unsigned long max_bits; /* log2 of largest supported purge page-size */
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2005-04-17 06:20:36 +08:00
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} purge;
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struct ia64_ctx ia64_ctx = {
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2007-04-16 01:21:23 +08:00
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.lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
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.next = 1,
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.max_ctx = ~0U
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2005-04-17 06:20:36 +08:00
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};
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DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
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2005-11-01 05:44:47 +08:00
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/*
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* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
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* Called after cpu_init() has setup ia64_ctx.max_ctx based on
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* maximum RID that is supported by boot CPU.
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*/
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void __init
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mmu_context_init (void)
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{
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ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
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ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
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}
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2005-04-17 06:20:36 +08:00
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/*
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* Acquire the ia64_ctx.lock before calling this function!
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*/
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void
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wrap_mmu_context (struct mm_struct *mm)
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{
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2005-10-30 09:47:04 +08:00
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int i, cpu;
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2005-11-01 05:44:47 +08:00
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unsigned long flush_bit;
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2005-04-17 06:20:36 +08:00
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2005-11-01 05:44:47 +08:00
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for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
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flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
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ia64_ctx.bitmap[i] ^= flush_bit;
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2005-04-17 06:20:36 +08:00
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}
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2005-11-01 05:44:47 +08:00
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/* use offset at 300 to skip daemons */
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ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, 300);
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ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, ia64_ctx.next);
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2005-10-30 09:47:04 +08:00
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/*
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* can't call flush_tlb_all() here because of race condition
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* with O(1) scheduler [EF]
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*/
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cpu = get_cpu(); /* prevent preemption/migration */
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for_each_online_cpu(i)
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if (i != cpu)
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per_cpu(ia64_need_tlb_flush, i) = 1;
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put_cpu();
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2005-04-17 06:20:36 +08:00
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local_flush_tlb_all();
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}
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void
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2005-10-30 09:47:04 +08:00
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ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long nbits)
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2005-04-17 06:20:36 +08:00
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{
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static DEFINE_SPINLOCK(ptcg_lock);
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2007-12-13 23:03:07 +08:00
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struct mm_struct *active_mm = current->active_mm;
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if (mm != active_mm) {
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/* Restore region IDs for mm */
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if (mm && active_mm) {
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activate_context(mm);
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} else {
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flush_tlb_all();
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return;
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}
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2005-10-28 04:41:04 +08:00
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}
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2005-04-17 06:20:36 +08:00
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/* HW requires global serialization of ptc.ga. */
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spin_lock(&ptcg_lock);
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{
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do {
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/*
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* Flush ALAT entries also.
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*/
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ia64_ptcga(start, (nbits<<2));
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ia64_srlz_i();
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start += (1UL << nbits);
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} while (start < end);
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}
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spin_unlock(&ptcg_lock);
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2007-12-13 23:03:07 +08:00
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if (mm != active_mm) {
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activate_context(active_mm);
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}
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2005-04-17 06:20:36 +08:00
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}
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void
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local_flush_tlb_all (void)
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{
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unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
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addr = local_cpu_data->ptce_base;
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count0 = local_cpu_data->ptce_count[0];
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count1 = local_cpu_data->ptce_count[1];
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stride0 = local_cpu_data->ptce_stride[0];
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stride1 = local_cpu_data->ptce_stride[1];
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local_irq_save(flags);
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for (i = 0; i < count0; ++i) {
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for (j = 0; j < count1; ++j) {
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ia64_ptce(addr);
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addr += stride1;
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}
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addr += stride0;
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}
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local_irq_restore(flags);
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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void
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2005-10-30 09:47:04 +08:00
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flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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2005-04-17 06:20:36 +08:00
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long size = end - start;
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unsigned long nbits;
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2005-10-28 04:41:04 +08:00
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#ifndef CONFIG_SMP
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2005-04-17 06:20:36 +08:00
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if (mm != current->active_mm) {
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mm->context = 0;
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return;
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}
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2005-10-28 04:41:04 +08:00
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#endif
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2005-04-17 06:20:36 +08:00
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nbits = ia64_fls(size + 0xfff);
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2005-10-30 09:47:04 +08:00
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while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
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(nbits < purge.max_bits))
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2005-04-17 06:20:36 +08:00
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++nbits;
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if (nbits > purge.max_bits)
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nbits = purge.max_bits;
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start &= ~((1UL << nbits) - 1);
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2005-10-30 09:16:28 +08:00
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preempt_disable();
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2006-03-07 06:12:54 +08:00
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#ifdef CONFIG_SMP
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if (mm != current->active_mm || cpus_weight(mm->cpu_vm_mask) != 1) {
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platform_global_tlb_purge(mm, start, end, nbits);
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preempt_enable();
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return;
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}
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#endif
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2005-04-17 06:20:36 +08:00
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do {
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ia64_ptcl(start, (nbits<<2));
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start += (1UL << nbits);
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} while (start < end);
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2005-10-30 09:16:28 +08:00
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preempt_enable();
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2005-04-17 06:20:36 +08:00
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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EXPORT_SYMBOL(flush_tlb_range);
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void __devinit
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ia64_tlb_init (void)
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{
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2007-07-11 23:26:30 +08:00
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ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
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2005-04-17 06:20:36 +08:00
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unsigned long tr_pgbits;
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long status;
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if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
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2007-11-20 09:47:53 +08:00
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printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
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2005-04-17 06:20:36 +08:00
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"defaulting to architected purge page-sizes.\n", status);
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purge.mask = 0x115557000UL;
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}
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purge.max_bits = ia64_fls(purge.mask);
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ia64_get_ptce(&ptce_info);
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local_cpu_data->ptce_base = ptce_info.base;
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local_cpu_data->ptce_count[0] = ptce_info.count[0];
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local_cpu_data->ptce_count[1] = ptce_info.count[1];
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local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
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local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
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2005-10-30 09:47:04 +08:00
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local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
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2005-04-17 06:20:36 +08:00
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}
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