2009-09-28 11:16:01 +08:00
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/*
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* bfin_serial.h - Blackfin UART/Serial definitions
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*
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* Copyright 2006-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_ASM_SERIAL_H__
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#define __BFIN_ASM_SERIAL_H__
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#include <linux/serial_core.h>
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2011-01-11 13:16:43 +08:00
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#include <linux/spinlock.h>
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2009-09-28 11:16:01 +08:00
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#include <mach/anomaly.h>
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#include <mach/bfin_serial.h>
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2009-09-09 18:46:19 +08:00
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
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defined(CONFIG_BFIN_UART1_CTSRTS) || \
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defined(CONFIG_BFIN_UART2_CTSRTS) || \
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defined(CONFIG_BFIN_UART3_CTSRTS)
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2012-05-16 17:37:24 +08:00
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# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
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2009-09-09 18:46:19 +08:00
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# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
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# else
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# define CONFIG_SERIAL_BFIN_CTSRTS
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# endif
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#endif
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2009-09-28 11:16:01 +08:00
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struct circ_buf;
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struct timer_list;
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struct work_struct;
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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2011-08-01 17:53:21 +08:00
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int tx_irq;
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int rx_irq;
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2009-09-28 11:16:01 +08:00
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int status_irq;
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#ifndef BFIN_UART_BF54X_STYLE
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unsigned int lsr;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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int tx_count;
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struct circ_buf rx_dma_buf;
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struct timer_list rx_dma_timer;
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int rx_dma_nrows;
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2011-01-11 13:16:43 +08:00
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spinlock_t rx_lock;
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2009-09-28 11:16:01 +08:00
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unsigned int tx_dma_channel;
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unsigned int rx_dma_channel;
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struct work_struct tx_dma_workqueue;
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#elif ANOMALY_05000363
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unsigned int anomaly_threshold;
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#endif
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#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
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defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
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int cts_pin;
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int rts_pin;
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#endif
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};
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2012-05-16 17:37:24 +08:00
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#ifdef BFIN_UART_BF60X_STYLE
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/* UART_CTL Masks */
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#define UCEN 0x1 /* Enable UARTx Clocks */
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#define LOOP_ENA 0x2 /* Loopback Mode Enable */
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#define UMOD_MDB 0x10 /* Enable MDB Mode */
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#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
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#define UMOD_MASK 0x30 /* Uart Mode Mask */
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#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
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#define WLS_MASK 0x300 /* Word length Select Mask */
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2012-04-26 16:51:29 +08:00
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#define WLS_OFFSET 8 /* Word length Select Offset */
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2012-05-16 17:37:24 +08:00
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#define STB 0x1000 /* Stop Bits */
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#define STBH 0x2000 /* Half Stop Bits */
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#define PEN 0x4000 /* Parity Enable */
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#define EPS 0x8000 /* Even Parity Select */
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#define STP 0x10000 /* Stick Parity */
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#define FPE 0x20000 /* Force Parity Error On Transmit */
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#define FFE 0x40000 /* Force Framing Error On Transmit */
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#define SB 0x80000 /* Set Break */
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2012-04-26 16:51:29 +08:00
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#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
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2012-05-16 17:37:24 +08:00
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#define FCPOL 0x400000 /* Flow Control Pin Polarity */
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#define RPOLC 0x800000 /* IrDA RX Polarity Change */
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#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
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#define MRTS 0x2000000 /* Manual Request To Send */
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#define XOFF 0x4000000 /* Transmitter Off */
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#define ARTS 0x8000000 /* Automatic Request To Send */
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#define ACTS 0x10000000 /* Automatic Clear To Send */
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#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
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#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
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/* UART_STAT Masks */
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* THR Empty */
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#define TEMT 0x80 /* TSR and UART_THR Empty */
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#define TFI 0x100 /* Transmission Finished Indicator */
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#define ASTKY 0x200 /* Address Sticky */
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#define ADDR 0x400 /* Address bit status */
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#define RO 0x800 /* Reception Ongoing */
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#define SCTS 0x1000 /* Sticky CTS */
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#define CTS 0x10000 /* Clear To Send */
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#define RFCS 0x20000 /* Receive FIFO Count Status */
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/* UART_CLOCK Masks */
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#define EDBO 0x80000000 /* Enable Devide by One */
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#else /* BFIN_UART_BF60X_STYLE */
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2009-09-28 11:16:01 +08:00
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/* UART_LCR Masks */
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#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
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2012-05-16 17:37:24 +08:00
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#define WLS_MASK 0x03 /* Word length Select Mask */
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2012-04-26 16:51:29 +08:00
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#define WLS_OFFSET 0 /* Word length Select Offset */
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2009-09-28 11:16:01 +08:00
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#define STB 0x04 /* Stop Bits */
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#define PEN 0x08 /* Parity Enable */
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#define EPS 0x10 /* Even Parity Select */
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#define STP 0x20 /* Stick Parity */
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#define SB 0x40 /* Set Break */
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#define DLAB 0x80 /* Divisor Latch Access */
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2012-04-26 16:51:29 +08:00
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#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
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2009-09-28 11:16:01 +08:00
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/* UART_LSR Masks */
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* THR Empty */
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#define TEMT 0x40 /* TSR and UART_THR Empty */
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#define TFI 0x80 /* Transmission Finished Indicator */
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/* UART_MCR Masks */
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#define XOFF 0x01 /* Transmitter Off */
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#define MRTS 0x02 /* Manual Request To Send */
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#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
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#define RFRT 0x08 /* Receive FIFO RTS Threshold */
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#define LOOP_ENA 0x10 /* Loopback Mode Enable */
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#define FCPOL 0x20 /* Flow Control Pin Polarity */
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#define ARTS 0x40 /* Automatic Request To Send */
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#define ACTS 0x80 /* Automatic Clear To Send */
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/* UART_MSR Masks */
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#define SCTS 0x01 /* Sticky CTS */
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#define CTS 0x10 /* Clear To Send */
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#define RFCS 0x20 /* Receive FIFO Count Status */
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/* UART_GCTL Masks */
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#define UCEN 0x01 /* Enable UARTx Clocks */
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2012-05-16 17:37:24 +08:00
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#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
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#define UMOD_MASK 0x02 /* Uart Mode Mask */
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2009-09-28 11:16:01 +08:00
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#define TPOLC 0x04 /* IrDA TX Polarity Change */
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#define RPOLC 0x08 /* IrDA RX Polarity Change */
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#define FPE 0x10 /* Force Parity Error On Transmit */
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#define FFE 0x20 /* Force Framing Error On Transmit */
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2012-05-16 17:37:24 +08:00
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#endif /* BFIN_UART_BF60X_STYLE */
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/* UART_IER Masks */
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#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
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#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
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#define ELSI 0x04 /* Enable RX Status Interrupt */
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#define EDSSI 0x08 /* Enable Modem Status Interrupt */
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#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
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#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
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#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
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#if defined(BFIN_UART_BF60X_STYLE)
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# define OFFSET_REDIV 0x00 /* Version ID Register */
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# define OFFSET_CTL 0x04 /* Control Register */
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# define OFFSET_STAT 0x08 /* Status Register */
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# define OFFSET_SCR 0x0C /* SCR Scratch Register */
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# define OFFSET_CLK 0x10 /* Clock Rate Register */
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# define OFFSET_IER 0x14 /* Interrupt Enable Register */
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# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
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# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
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# define OFFSET_RBR 0x20 /* Receive Buffer register */
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# define OFFSET_THR 0x24 /* Transmit Holding register */
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#elif defined(BFIN_UART_BF54X_STYLE)
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2009-09-28 11:16:01 +08:00
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# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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# define OFFSET_GCTL 0x08 /* Global Control Register */
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# define OFFSET_LCR 0x0C /* Line Control Register */
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# define OFFSET_MCR 0x10 /* Modem Control Register */
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# define OFFSET_LSR 0x14 /* Line Status Register */
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# define OFFSET_MSR 0x18 /* Modem Status Register */
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# define OFFSET_SCR 0x1C /* SCR Scratch Register */
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# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
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# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
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# define OFFSET_THR 0x28 /* Transmit Holding register */
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# define OFFSET_RBR 0x2C /* Receive Buffer register */
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#else /* BF533 style */
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# define OFFSET_THR 0x00 /* Transmit Holding register */
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# define OFFSET_RBR 0x00 /* Receive Buffer register */
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# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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# define OFFSET_IER 0x04 /* Interrupt Enable Register */
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# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
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# define OFFSET_LCR 0x0C /* Line Control Register */
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# define OFFSET_MCR 0x10 /* Modem Control Register */
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# define OFFSET_LSR 0x14 /* Line Status Register */
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# define OFFSET_MSR 0x18 /* Modem Status Register */
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# define OFFSET_SCR 0x1C /* SCR Scratch Register */
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# define OFFSET_GCTL 0x24 /* Global Control Register */
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/* code should not need IIR, so force build error if they use it */
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# undef OFFSET_IIR
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#endif
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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struct bfin_uart_regs {
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2012-05-16 17:37:24 +08:00
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#if defined(BFIN_UART_BF60X_STYLE)
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u32 revid;
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u32 ctl;
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u32 stat;
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u32 scr;
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u32 clk;
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u32 ier;
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u32 ier_set;
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u32 ier_clear;
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u32 rbr;
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u32 thr;
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u32 taip;
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u32 tsr;
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u32 rsr;
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u32 txdiv;
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u32 rxdiv;
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#elif defined(BFIN_UART_BF54X_STYLE)
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2009-09-28 11:16:01 +08:00
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__BFP(dll);
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__BFP(dlh);
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__BFP(gctl);
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__BFP(lcr);
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__BFP(mcr);
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__BFP(lsr);
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__BFP(msr);
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__BFP(scr);
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__BFP(ier_set);
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__BFP(ier_clear);
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__BFP(thr);
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__BFP(rbr);
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#else
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union {
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u16 dll;
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u16 thr;
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const u16 rbr;
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};
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const u16 __pad0;
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union {
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u16 dlh;
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u16 ier;
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};
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const u16 __pad1;
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const __BFP(iir);
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__BFP(lcr);
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__BFP(mcr);
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__BFP(lsr);
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__BFP(msr);
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__BFP(scr);
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const u32 __pad2;
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__BFP(gctl);
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#endif
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};
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#undef __BFP
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2012-05-16 17:37:24 +08:00
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#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
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/*
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2009-09-28 11:16:01 +08:00
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#ifndef port_membase
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2010-10-27 15:41:03 +08:00
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# define port_membase(p) 0
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2009-09-28 11:16:01 +08:00
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#endif
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2012-05-16 17:37:24 +08:00
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*/
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#ifdef BFIN_UART_BF60X_STYLE
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#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
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#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
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#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
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#define UART_GET_GCTL(p) UART_GET_CTL(p)
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#define UART_GET_LCR(p) UART_GET_CTL(p)
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#define UART_GET_MCR(p) UART_GET_CTL(p)
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#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
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#define UART_GET_MSR(p) UART_GET_STAT(p)
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#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
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#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
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#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
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#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
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#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
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#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
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#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
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#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
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#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
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#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
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#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
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#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
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#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
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#define UART_GET_LSR(p) UART_GET_STAT(p)
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#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
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/* This handles hard CTS/RTS */
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#define BFIN_UART_CTSRTS_HARD
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#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
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#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
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#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
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#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
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#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
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#else /* BFIN_UART_BF60X_STYLE */
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2009-09-28 11:16:01 +08:00
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#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
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#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
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#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
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2012-05-16 17:37:24 +08:00
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#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
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2009-09-28 11:16:01 +08:00
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#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
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#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
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#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
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#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
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#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
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#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
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#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
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2012-05-16 17:37:24 +08:00
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#define UART_PUT_CLK(p, v) do \
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{\
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UART_PUT_DLL(p, v & 0xFF); \
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UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
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2009-09-28 11:16:01 +08:00
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#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
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#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
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#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
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#ifdef BFIN_UART_BF54X_STYLE
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#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
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#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
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#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
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#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
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#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
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#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
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#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
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#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
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/* This handles hard CTS/RTS */
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2009-09-09 18:46:19 +08:00
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#define BFIN_UART_CTSRTS_HARD
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2009-09-28 11:16:01 +08:00
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#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
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#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
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#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
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#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
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#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
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#else /* BF533 style */
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#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
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#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
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#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
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#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
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#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
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#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
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2012-05-16 17:37:24 +08:00
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#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
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#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
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/*
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2009-09-28 11:16:01 +08:00
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#ifndef put_lsr_cache
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2010-10-27 15:41:03 +08:00
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# define put_lsr_cache(p, v)
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2009-09-28 11:16:01 +08:00
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#endif
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#ifndef get_lsr_cache
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2010-10-27 15:41:03 +08:00
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# define get_lsr_cache(p) 0
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2009-09-28 11:16:01 +08:00
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#endif
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2012-05-16 17:37:24 +08:00
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*/
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2009-09-28 11:16:01 +08:00
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/* The hardware clears the LSR bits upon read, so we need to cache
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* some of the more fun bits in software so they don't get lost
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* when checking the LSR in other code paths (TX).
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*/
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static inline void UART_CLEAR_LSR(void *p)
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{
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put_lsr_cache(p, 0);
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bfin_write16(port_membase(p) + OFFSET_LSR, -1);
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}
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static inline unsigned int UART_GET_LSR(void *p)
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{
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unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
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put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
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return lsr | get_lsr_cache(p);
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}
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static inline void UART_PUT_LSR(void *p, uint16_t val)
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{
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put_lsr_cache(p, get_lsr_cache(p) & ~val);
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}
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/* This handles soft CTS/RTS */
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#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
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#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
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#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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|
2012-05-16 17:37:24 +08:00
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|
#endif /* BFIN_UART_BF54X_STYLE */
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#endif /* BFIN_UART_BF60X_STYLE */
|
2009-09-28 11:16:01 +08:00
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#ifndef BFIN_UART_TX_FIFO_SIZE
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# define BFIN_UART_TX_FIFO_SIZE 2
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#endif
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#endif /* __BFIN_ASM_SERIAL_H__ */
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