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33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
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NVIDIA Tegra30 AHUB (Audio Hub)
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Required properties:
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- compatible : "nvidia,tegra30-ahub"
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- reg : Should contain the register physical address and length for each of
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the AHUB's APBIF registers and the AHUB's own registers.
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- interrupts : Should contain AHUB interrupt
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- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
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request selector for the first APBIF channel.
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- ranges : The bus address mapping for the configlink register bus.
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Can be empty since the mapping is 1:1.
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- #address-cells : For the configlink bus. Should be <1>;
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- #size-cells : For the configlink bus. Should be <1>.
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AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
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For RX CIFs, the numbers indicate the register number within AHUB routing
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register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
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For TX CIFs, the numbers indicate the bit position within the AHUB routing
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registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
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Example:
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ahub@70080000 {
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compatible = "nvidia,tegra30-ahub";
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reg = <0x70080000 0x200 0x70080200 0x100>;
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interrupts = < 0 103 0x04 >;
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nvidia,dma-request-selector = <&apbdma 1>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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