2018-09-08 19:07:18 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
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* pinctrl-bindings.txt for MediaTek SoC.
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*
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* Copyright (C) 2017-2018 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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2018-09-19 06:03:13 +08:00
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#include <linux/gpio/driver.h>
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2018-09-08 19:07:18 +08:00
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#include "pinctrl-moore.h"
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#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
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/* Custom pinconf parameters */
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#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
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#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
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2018-09-08 19:07:25 +08:00
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#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
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#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
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2018-09-08 19:07:18 +08:00
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static const struct pinconf_generic_params mtk_custom_bindings[] = {
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{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
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{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
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2018-09-08 19:07:25 +08:00
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{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
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{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
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2018-09-08 19:07:18 +08:00
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};
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#ifdef CONFIG_DEBUG_FS
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static const struct pin_config_item mtk_conf_items[] = {
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PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
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PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
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2018-09-08 19:07:25 +08:00
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PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
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PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
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2018-09-08 19:07:18 +08:00
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};
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#endif
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static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned int group)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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struct function_desc *func;
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struct group_desc *grp;
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int i;
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func = pinmux_generic_get_function(pctldev, selector);
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if (!func)
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return -EINVAL;
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grp = pinctrl_generic_get_group(pctldev, group);
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if (!grp)
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return -EINVAL;
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dev_dbg(pctldev->dev, "enable function %s group %s\n",
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func->name, grp->name);
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for (i = 0; i < grp->num_pins; i++) {
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2018-09-08 19:07:29 +08:00
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const struct mtk_pin_desc *desc;
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2018-09-08 19:07:18 +08:00
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int *pin_modes = grp->data;
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2018-09-08 19:07:29 +08:00
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int pin = grp->pins[i];
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2018-09-08 19:07:18 +08:00
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2018-09-08 19:07:29 +08:00
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
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2018-09-08 19:07:18 +08:00
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pin_modes[i]);
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}
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return 0;
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}
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static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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2018-09-08 19:07:29 +08:00
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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2018-09-08 19:07:18 +08:00
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2018-09-08 19:07:29 +08:00
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return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
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hw->soc->gpio_m);
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2018-09-08 19:07:18 +08:00
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}
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static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin, bool input)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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2018-09-08 19:07:29 +08:00
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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2018-09-08 19:07:18 +08:00
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/* hardware would take 0 as input direction */
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2018-09-08 19:07:29 +08:00
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return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
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2018-09-08 19:07:18 +08:00
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}
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static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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u32 param = pinconf_to_config_param(*config);
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int val, val2, err, reg, ret = 1;
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2018-09-08 19:07:22 +08:00
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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2018-09-08 19:07:18 +08:00
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_disable_get) {
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err = hw->soc->bias_disable_get(hw, desc, &ret);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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2018-09-08 19:07:18 +08:00
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_get) {
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err = hw->soc->bias_get(hw, desc, 1, &ret);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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break;
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2018-09-08 19:07:18 +08:00
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case PIN_CONFIG_BIAS_PULL_DOWN:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_get) {
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err = hw->soc->bias_get(hw, desc, 0, &ret);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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break;
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2018-09-08 19:07:18 +08:00
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case PIN_CONFIG_SLEW_RATE:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
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2018-09-08 19:07:18 +08:00
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if (err)
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return err;
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if (!val)
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return -EINVAL;
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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case PIN_CONFIG_OUTPUT_ENABLE:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
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2018-09-08 19:07:18 +08:00
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if (err)
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return err;
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/* HW takes input mode as zero; output mode as non-zero */
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if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
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(!val && param == PIN_CONFIG_OUTPUT_ENABLE))
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return -EINVAL;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
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2018-09-08 19:07:18 +08:00
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if (err)
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return err;
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
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2018-09-08 19:07:18 +08:00
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if (err)
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return err;
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if (val || !val2)
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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2018-09-08 19:07:22 +08:00
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if (hw->soc->drive_get) {
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err = hw->soc->drive_get(hw, desc, &ret);
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if (err)
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return err;
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} else {
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err = -ENOTSUPP;
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}
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2018-09-08 19:07:18 +08:00
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break;
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case MTK_PIN_CONFIG_TDSEL:
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case MTK_PIN_CONFIG_RDSEL:
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reg = (param == MTK_PIN_CONFIG_TDSEL) ?
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PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_get_value(hw, desc, reg, &val);
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2018-09-08 19:07:18 +08:00
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if (err)
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return err;
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ret = val;
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2018-09-08 19:07:25 +08:00
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break;
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case MTK_PIN_CONFIG_PU_ADV:
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case MTK_PIN_CONFIG_PD_ADV:
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if (hw->soc->adv_pull_get) {
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bool pullup;
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pullup = param == MTK_PIN_CONFIG_PU_ADV;
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err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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2018-09-08 19:07:18 +08:00
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, ret);
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return 0;
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}
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static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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2018-09-08 19:07:22 +08:00
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const struct mtk_pin_desc *desc;
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2018-09-08 19:07:18 +08:00
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u32 reg, param, arg;
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int cfg, err = 0;
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2018-09-08 19:07:22 +08:00
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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2018-09-08 19:07:18 +08:00
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for (cfg = 0; cfg < num_configs; cfg++) {
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param = pinconf_to_config_param(configs[cfg]);
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arg = pinconf_to_config_argument(configs[cfg]);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_disable_set) {
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err = hw->soc->bias_disable_set(hw, desc);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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break;
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2018-09-08 19:07:18 +08:00
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case PIN_CONFIG_BIAS_PULL_UP:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_set) {
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err = hw->soc->bias_set(hw, desc, 1);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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break;
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2018-09-08 19:07:18 +08:00
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case PIN_CONFIG_BIAS_PULL_DOWN:
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2018-09-08 19:07:24 +08:00
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if (hw->soc->bias_set) {
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err = hw->soc->bias_set(hw, desc, 0);
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if (err)
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return err;
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} else {
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return -ENOTSUPP;
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}
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2018-09-08 19:07:18 +08:00
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break;
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case PIN_CONFIG_OUTPUT_ENABLE:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
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2018-09-08 19:07:18 +08:00
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MTK_DISABLE);
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if (err)
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goto err;
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2018-09-08 19:07:26 +08:00
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
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2018-09-08 19:07:26 +08:00
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MTK_OUTPUT);
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if (err)
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goto err;
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break;
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2018-09-08 19:07:18 +08:00
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case PIN_CONFIG_INPUT_ENABLE:
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2018-09-08 19:07:26 +08:00
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if (hw->soc->ies_present) {
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2018-09-08 19:07:29 +08:00
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mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
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2018-09-08 19:07:26 +08:00
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MTK_ENABLE);
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}
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
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2018-09-08 19:07:26 +08:00
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MTK_INPUT);
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if (err)
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goto err;
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break;
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case PIN_CONFIG_SLEW_RATE:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
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2018-09-08 19:07:26 +08:00
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arg);
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2018-09-08 19:07:18 +08:00
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if (err)
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goto err;
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break;
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case PIN_CONFIG_OUTPUT:
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
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2018-09-08 19:07:18 +08:00
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MTK_OUTPUT);
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if (err)
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goto err;
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
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2018-09-08 19:07:18 +08:00
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arg);
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if (err)
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goto err;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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/* arg = 1: Input mode & SMT enable ;
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* arg = 0: Output mode & SMT disable
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*/
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arg = arg ? 2 : 1;
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
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2018-09-08 19:07:18 +08:00
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arg & 1);
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if (err)
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goto err;
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2018-09-08 19:07:29 +08:00
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err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
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2018-09-08 19:07:18 +08:00
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!!(arg & 2));
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if (err)
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goto err;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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2018-09-08 19:07:22 +08:00
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if (hw->soc->drive_set) {
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err = hw->soc->drive_set(hw, desc, arg);
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2018-11-01 02:42:41 +08:00
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if (err)
|
|
|
|
return err;
|
2018-09-08 19:07:18 +08:00
|
|
|
} else {
|
|
|
|
err = -ENOTSUPP;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MTK_PIN_CONFIG_TDSEL:
|
|
|
|
case MTK_PIN_CONFIG_RDSEL:
|
|
|
|
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
|
|
|
|
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
|
|
|
|
|
2018-09-08 19:07:29 +08:00
|
|
|
err = mtk_hw_set_value(hw, desc, reg, arg);
|
2018-09-08 19:07:18 +08:00
|
|
|
if (err)
|
|
|
|
goto err;
|
|
|
|
break;
|
2018-09-08 19:07:25 +08:00
|
|
|
case MTK_PIN_CONFIG_PU_ADV:
|
|
|
|
case MTK_PIN_CONFIG_PD_ADV:
|
|
|
|
if (hw->soc->adv_pull_set) {
|
|
|
|
bool pullup;
|
|
|
|
|
|
|
|
pullup = param == MTK_PIN_CONFIG_PU_ADV;
|
|
|
|
err = hw->soc->adv_pull_set(hw, desc, pullup,
|
|
|
|
arg);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
} else {
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
break;
|
2018-09-08 19:07:18 +08:00
|
|
|
default:
|
|
|
|
err = -ENOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
err:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int group, unsigned long *config)
|
|
|
|
{
|
|
|
|
const unsigned int *pins;
|
|
|
|
unsigned int i, npins, old = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < npins; i++) {
|
|
|
|
if (mtk_pinconf_get(pctldev, pins[i], config))
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
/* configs do not match between two pins */
|
|
|
|
if (i && old != *config)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
old = *config;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int group, unsigned long *configs,
|
|
|
|
unsigned int num_configs)
|
|
|
|
{
|
|
|
|
const unsigned int *pins;
|
|
|
|
unsigned int i, npins;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < npins; i++) {
|
|
|
|
ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pinctrl_ops mtk_pctlops = {
|
|
|
|
.get_groups_count = pinctrl_generic_get_group_count,
|
|
|
|
.get_group_name = pinctrl_generic_get_group_name,
|
|
|
|
.get_group_pins = pinctrl_generic_get_group_pins,
|
|
|
|
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
|
|
|
|
.dt_free_map = pinconf_generic_dt_free_map,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct pinmux_ops mtk_pmxops = {
|
|
|
|
.get_functions_count = pinmux_generic_get_function_count,
|
|
|
|
.get_function_name = pinmux_generic_get_function_name,
|
|
|
|
.get_function_groups = pinmux_generic_get_function_groups,
|
|
|
|
.set_mux = mtk_pinmux_set_mux,
|
|
|
|
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
|
|
|
|
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
|
|
|
|
.strict = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct pinconf_ops mtk_confops = {
|
|
|
|
.is_generic = true,
|
|
|
|
.pin_config_get = mtk_pinconf_get,
|
|
|
|
.pin_config_set = mtk_pinconf_set,
|
|
|
|
.pin_config_group_get = mtk_pinconf_group_get,
|
|
|
|
.pin_config_group_set = mtk_pinconf_group_set,
|
|
|
|
.pin_config_config_dbg_show = pinconf_generic_dump_config,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pinctrl_desc mtk_desc = {
|
|
|
|
.name = PINCTRL_PINCTRL_DEV,
|
|
|
|
.pctlops = &mtk_pctlops,
|
|
|
|
.pmxops = &mtk_pmxops,
|
|
|
|
.confops = &mtk_confops,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
2018-09-08 19:07:29 +08:00
|
|
|
const struct mtk_pin_desc *desc;
|
2018-09-08 19:07:18 +08:00
|
|
|
int value, err;
|
|
|
|
|
2018-09-08 19:07:29 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
|
2018-09-08 19:07:18 +08:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
return !!value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
2018-09-08 19:07:29 +08:00
|
|
|
const struct mtk_pin_desc *desc;
|
2018-09-08 19:07:18 +08:00
|
|
|
|
2018-09-08 19:07:29 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
2018-09-08 19:07:18 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
|
|
|
|
{
|
|
|
|
return pinctrl_gpio_direction_input(chip->base + gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
|
|
|
|
int value)
|
|
|
|
{
|
|
|
|
mtk_gpio_set(chip, gpio, value);
|
|
|
|
|
|
|
|
return pinctrl_gpio_direction_output(chip->base + gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
2018-09-08 19:07:20 +08:00
|
|
|
const struct mtk_pin_desc *desc;
|
2018-09-08 19:07:18 +08:00
|
|
|
|
|
|
|
if (!hw->eint)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
2018-09-08 19:07:20 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
|
2018-09-08 19:07:18 +08:00
|
|
|
|
2018-09-25 17:55:56 +08:00
|
|
|
if (desc->eint.eint_n == (u16)EINT_NA)
|
2018-09-08 19:07:20 +08:00
|
|
|
return -ENOTSUPP;
|
|
|
|
|
2018-09-08 19:07:32 +08:00
|
|
|
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
|
2018-09-08 19:07:18 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|
|
|
unsigned long config)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
2018-09-08 19:07:20 +08:00
|
|
|
const struct mtk_pin_desc *desc;
|
2018-09-08 19:07:18 +08:00
|
|
|
u32 debounce;
|
|
|
|
|
2018-09-08 19:07:20 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
|
|
|
|
|
2018-09-08 19:07:18 +08:00
|
|
|
if (!hw->eint ||
|
2018-09-08 19:07:20 +08:00
|
|
|
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
|
2018-09-25 17:55:56 +08:00
|
|
|
desc->eint.eint_n == (u16)EINT_NA)
|
2018-09-08 19:07:18 +08:00
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
debounce = pinconf_to_config_argument(config);
|
|
|
|
|
2018-09-08 19:07:32 +08:00
|
|
|
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
|
2018-09-08 19:07:18 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
|
|
|
{
|
|
|
|
struct gpio_chip *chip = &hw->chip;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
chip->label = PINCTRL_PINCTRL_DEV;
|
|
|
|
chip->parent = hw->dev;
|
|
|
|
chip->request = gpiochip_generic_request;
|
|
|
|
chip->free = gpiochip_generic_free;
|
|
|
|
chip->direction_input = mtk_gpio_direction_input;
|
|
|
|
chip->direction_output = mtk_gpio_direction_output;
|
|
|
|
chip->get = mtk_gpio_get;
|
|
|
|
chip->set = mtk_gpio_set;
|
|
|
|
chip->to_irq = mtk_gpio_to_irq,
|
|
|
|
chip->set_config = mtk_gpio_set_config,
|
|
|
|
chip->base = -1;
|
|
|
|
chip->ngpio = hw->soc->npins;
|
|
|
|
chip->of_node = np;
|
|
|
|
chip->of_gpio_n_cells = 2;
|
|
|
|
|
|
|
|
ret = gpiochip_add_data(chip, hw);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Just for backward compatible for these old pinctrl nodes without
|
|
|
|
* "gpio-ranges" property. Otherwise, called directly from a
|
|
|
|
* DeviceTree-supported pinctrl driver is DEPRECATED.
|
|
|
|
* Please see Section 2.1 of
|
|
|
|
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
|
|
|
|
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
|
|
|
|
*/
|
|
|
|
if (!of_find_property(np, "gpio-ranges", NULL)) {
|
|
|
|
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
|
|
|
|
chip->ngpio);
|
|
|
|
if (ret < 0) {
|
|
|
|
gpiochip_remove(chip);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_build_groups(struct mtk_pinctrl *hw)
|
|
|
|
{
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->ngrps; i++) {
|
|
|
|
const struct group_desc *group = hw->soc->grps + i;
|
|
|
|
|
|
|
|
err = pinctrl_generic_add_group(hw->pctrl, group->name,
|
|
|
|
group->pins, group->num_pins,
|
|
|
|
group->data);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(hw->dev, "Failed to register group %s\n",
|
|
|
|
group->name);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_build_functions(struct mtk_pinctrl *hw)
|
|
|
|
{
|
|
|
|
int i, err;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->nfuncs ; i++) {
|
|
|
|
const struct function_desc *func = hw->soc->funcs + i;
|
|
|
|
|
|
|
|
err = pinmux_generic_add_function(hw->pctrl, func->name,
|
|
|
|
func->group_names,
|
|
|
|
func->num_group_names,
|
|
|
|
func->data);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(hw->dev, "Failed to register function %s\n",
|
|
|
|
func->name);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
|
|
|
const struct mtk_pin_soc *soc)
|
|
|
|
{
|
2018-09-08 19:07:32 +08:00
|
|
|
struct pinctrl_pin_desc *pins;
|
2018-09-08 19:07:18 +08:00
|
|
|
struct resource *res;
|
|
|
|
struct mtk_pinctrl *hw;
|
2018-09-08 19:07:30 +08:00
|
|
|
int err, i;
|
2018-09-08 19:07:18 +08:00
|
|
|
|
|
|
|
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
|
|
|
|
if (!hw)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
hw->soc = soc;
|
2018-09-08 19:07:30 +08:00
|
|
|
hw->dev = &pdev->dev;
|
2018-09-08 19:07:18 +08:00
|
|
|
|
2018-09-08 19:07:30 +08:00
|
|
|
if (!hw->soc->nbase_names) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"SoC should be assigned at least one register base\n");
|
|
|
|
return -EINVAL;
|
2018-09-08 19:07:18 +08:00
|
|
|
}
|
|
|
|
|
2018-09-08 19:07:30 +08:00
|
|
|
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
|
|
|
|
sizeof(*hw->base), GFP_KERNEL);
|
2018-09-20 14:21:50 +08:00
|
|
|
if (!hw->base)
|
|
|
|
return -ENOMEM;
|
2018-09-08 19:07:18 +08:00
|
|
|
|
2018-09-08 19:07:30 +08:00
|
|
|
for (i = 0; i < hw->soc->nbase_names; i++) {
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
|
|
hw->soc->base_names[i]);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(&pdev->dev, "missing IO resource\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(hw->base[i]))
|
|
|
|
return PTR_ERR(hw->base[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
hw->nbase = hw->soc->nbase_names;
|
|
|
|
|
2018-09-08 19:07:32 +08:00
|
|
|
/* Copy from internal struct mtk_pin_desc to register to the core */
|
|
|
|
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
|
|
|
|
GFP_KERNEL);
|
2018-09-20 14:21:50 +08:00
|
|
|
if (!pins)
|
|
|
|
return -ENOMEM;
|
2018-09-08 19:07:32 +08:00
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->npins; i++) {
|
|
|
|
pins[i].number = hw->soc->pins[i].number;
|
|
|
|
pins[i].name = hw->soc->pins[i].name;
|
|
|
|
}
|
|
|
|
|
2018-09-08 19:07:18 +08:00
|
|
|
/* Setup pins descriptions per SoC types */
|
2018-09-08 19:07:32 +08:00
|
|
|
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
|
2018-09-08 19:07:18 +08:00
|
|
|
mtk_desc.npins = hw->soc->npins;
|
|
|
|
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
|
|
|
|
mtk_desc.custom_params = mtk_custom_bindings;
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
mtk_desc.custom_conf_items = mtk_conf_items;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
|
|
|
|
&hw->pctrl);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Setup groups descriptions per SoC types */
|
|
|
|
err = mtk_build_groups(hw);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to build groups\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup functions descriptions per SoC types */
|
|
|
|
err = mtk_build_functions(hw);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to build functions\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
|
|
|
|
* until all groups and functions are being added one.
|
|
|
|
*/
|
|
|
|
err = pinctrl_enable(hw->pctrl);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = mtk_build_eint(hw, pdev);
|
|
|
|
if (err)
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
"Failed to add EINT, but pinctrl still can work\n");
|
|
|
|
|
|
|
|
/* Build gpiochip should be after pinctrl_enable is done */
|
|
|
|
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|