mirror of https://gitee.com/openkylin/linux.git
300 lines
10 KiB
ArmAsm
300 lines
10 KiB
ArmAsm
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/*
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* Fast SHA-1 implementation for SPE instruction set (PPC)
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*
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* This code makes use of the SPE SIMD instruction set as defined in
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* http://cache.freescale.com/files/32bit/doc/ref_manual/SPEPIM.pdf
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* Implementation is based on optimization guide notes from
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* http://cache.freescale.com/files/32bit/doc/app_note/AN2665.pdf
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*
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* Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#define rHP r3 /* pointer to hash value */
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#define rWP r4 /* pointer to input */
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#define rKP r5 /* pointer to constants */
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#define rW0 r14 /* 64 bit round words */
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#define rW1 r15
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#define rW2 r16
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#define rW3 r17
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#define rW4 r18
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#define rW5 r19
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#define rW6 r20
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#define rW7 r21
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#define rH0 r6 /* 32 bit hash values */
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#define rH1 r7
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#define rH2 r8
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#define rH3 r9
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#define rH4 r10
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#define rT0 r22 /* 64 bit temporary */
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#define rT1 r0 /* 32 bit temporaries */
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#define rT2 r11
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#define rT3 r12
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#define rK r23 /* 64 bit constant in volatile register */
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#define LOAD_K01
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#define LOAD_K11 \
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evlwwsplat rK,0(rKP);
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#define LOAD_K21 \
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evlwwsplat rK,4(rKP);
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#define LOAD_K31 \
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evlwwsplat rK,8(rKP);
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#define LOAD_K41 \
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evlwwsplat rK,12(rKP);
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#define INITIALIZE \
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stwu r1,-128(r1); /* create stack frame */ \
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evstdw r14,8(r1); /* We must save non volatile */ \
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evstdw r15,16(r1); /* registers. Take the chance */ \
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evstdw r16,24(r1); /* and save the SPE part too */ \
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evstdw r17,32(r1); \
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evstdw r18,40(r1); \
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evstdw r19,48(r1); \
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evstdw r20,56(r1); \
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evstdw r21,64(r1); \
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evstdw r22,72(r1); \
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evstdw r23,80(r1);
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#define FINALIZE \
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evldw r14,8(r1); /* restore SPE registers */ \
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evldw r15,16(r1); \
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evldw r16,24(r1); \
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evldw r17,32(r1); \
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evldw r18,40(r1); \
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evldw r19,48(r1); \
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evldw r20,56(r1); \
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evldw r21,64(r1); \
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evldw r22,72(r1); \
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evldw r23,80(r1); \
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xor r0,r0,r0; \
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stw r0,8(r1); /* Delete sensitive data */ \
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stw r0,16(r1); /* that we might have pushed */ \
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stw r0,24(r1); /* from other context that runs */ \
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stw r0,32(r1); /* the same code. Assume that */ \
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stw r0,40(r1); /* the lower part of the GPRs */ \
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stw r0,48(r1); /* were already overwritten on */ \
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stw r0,56(r1); /* the way down to here */ \
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stw r0,64(r1); \
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stw r0,72(r1); \
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stw r0,80(r1); \
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addi r1,r1,128; /* cleanup stack frame */
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#ifdef __BIG_ENDIAN__
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#define LOAD_DATA(reg, off) \
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lwz reg,off(rWP); /* load data */
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#define NEXT_BLOCK \
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addi rWP,rWP,64; /* increment per block */
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#else
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#define LOAD_DATA(reg, off) \
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lwbrx reg,0,rWP; /* load data */ \
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addi rWP,rWP,4; /* increment per word */
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#define NEXT_BLOCK /* nothing to do */
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#endif
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#define R_00_15(a, b, c, d, e, w0, w1, k, off) \
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LOAD_DATA(w0, off) /* 1: W */ \
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and rT2,b,c; /* 1: F' = B and C */ \
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LOAD_K##k##1 \
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andc rT1,d,b; /* 1: F" = ~B and D */ \
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rotrwi rT0,a,27; /* 1: A' = A rotl 5 */ \
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or rT2,rT2,rT1; /* 1: F = F' or F" */ \
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add e,e,rT0; /* 1: E = E + A' */ \
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rotrwi b,b,2; /* 1: B = B rotl 30 */ \
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add e,e,w0; /* 1: E = E + W */ \
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LOAD_DATA(w1, off+4) /* 2: W */ \
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add e,e,rT2; /* 1: E = E + F */ \
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and rT1,a,b; /* 2: F' = B and C */ \
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add e,e,rK; /* 1: E = E + K */ \
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andc rT2,c,a; /* 2: F" = ~B and D */ \
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add d,d,rK; /* 2: E = E + K */ \
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or rT2,rT2,rT1; /* 2: F = F' or F" */ \
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rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
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add d,d,w1; /* 2: E = E + W */ \
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rotrwi a,a,2; /* 2: B = B rotl 30 */ \
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add d,d,rT0; /* 2: E = E + A' */ \
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evmergelo w1,w1,w0; /* mix W[0]/W[1] */ \
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add d,d,rT2 /* 2: E = E + F */
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#define R_16_19(a, b, c, d, e, w0, w1, w4, w6, w7, k) \
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and rT2,b,c; /* 1: F' = B and C */ \
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evmergelohi rT0,w7,w6; /* W[-3] */ \
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andc rT1,d,b; /* 1: F" = ~B and D */ \
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evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
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or rT1,rT1,rT2; /* 1: F = F' or F" */ \
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evxor w0,w0,w4; /* W = W xor W[-8] */ \
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add e,e,rT1; /* 1: E = E + F */ \
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evxor w0,w0,w1; /* W = W xor W[-14] */ \
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rotrwi rT2,a,27; /* 1: A' = A rotl 5 */ \
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evrlwi w0,w0,1; /* W = W rotl 1 */ \
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add e,e,rT2; /* 1: E = E + A' */ \
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evaddw rT0,w0,rK; /* WK = W + K */ \
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rotrwi b,b,2; /* 1: B = B rotl 30 */ \
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LOAD_K##k##1 \
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evmergehi rT1,rT1,rT0; /* WK1/WK2 */ \
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add e,e,rT0; /* 1: E = E + WK */ \
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add d,d,rT1; /* 2: E = E + WK */ \
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and rT2,a,b; /* 2: F' = B and C */ \
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andc rT1,c,a; /* 2: F" = ~B and D */ \
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rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
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or rT1,rT1,rT2; /* 2: F = F' or F" */ \
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add d,d,rT0; /* 2: E = E + A' */ \
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rotrwi a,a,2; /* 2: B = B rotl 30 */ \
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add d,d,rT1 /* 2: E = E + F */
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#define R_20_39(a, b, c, d, e, w0, w1, w4, w6, w7, k) \
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evmergelohi rT0,w7,w6; /* W[-3] */ \
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xor rT2,b,c; /* 1: F' = B xor C */ \
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evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
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xor rT2,rT2,d; /* 1: F = F' xor D */ \
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evxor w0,w0,w4; /* W = W xor W[-8] */ \
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add e,e,rT2; /* 1: E = E + F */ \
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evxor w0,w0,w1; /* W = W xor W[-14] */ \
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rotrwi rT2,a,27; /* 1: A' = A rotl 5 */ \
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evrlwi w0,w0,1; /* W = W rotl 1 */ \
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add e,e,rT2; /* 1: E = E + A' */ \
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evaddw rT0,w0,rK; /* WK = W + K */ \
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rotrwi b,b,2; /* 1: B = B rotl 30 */ \
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LOAD_K##k##1 \
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evmergehi rT1,rT1,rT0; /* WK1/WK2 */ \
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add e,e,rT0; /* 1: E = E + WK */ \
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xor rT2,a,b; /* 2: F' = B xor C */ \
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add d,d,rT1; /* 2: E = E + WK */ \
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xor rT2,rT2,c; /* 2: F = F' xor D */ \
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rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
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add d,d,rT2; /* 2: E = E + F */ \
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rotrwi a,a,2; /* 2: B = B rotl 30 */ \
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add d,d,rT0 /* 2: E = E + A' */
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#define R_40_59(a, b, c, d, e, w0, w1, w4, w6, w7, k) \
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and rT2,b,c; /* 1: F' = B and C */ \
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evmergelohi rT0,w7,w6; /* W[-3] */ \
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or rT1,b,c; /* 1: F" = B or C */ \
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evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
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and rT1,d,rT1; /* 1: F" = F" and D */ \
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evxor w0,w0,w4; /* W = W xor W[-8] */ \
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or rT2,rT2,rT1; /* 1: F = F' or F" */ \
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evxor w0,w0,w1; /* W = W xor W[-14] */ \
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add e,e,rT2; /* 1: E = E + F */ \
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evrlwi w0,w0,1; /* W = W rotl 1 */ \
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rotrwi rT2,a,27; /* 1: A' = A rotl 5 */ \
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evaddw rT0,w0,rK; /* WK = W + K */ \
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add e,e,rT2; /* 1: E = E + A' */ \
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LOAD_K##k##1 \
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evmergehi rT1,rT1,rT0; /* WK1/WK2 */ \
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rotrwi b,b,2; /* 1: B = B rotl 30 */ \
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add e,e,rT0; /* 1: E = E + WK */ \
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and rT2,a,b; /* 2: F' = B and C */ \
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or rT0,a,b; /* 2: F" = B or C */ \
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add d,d,rT1; /* 2: E = E + WK */ \
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and rT0,c,rT0; /* 2: F" = F" and D */ \
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rotrwi a,a,2; /* 2: B = B rotl 30 */ \
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or rT2,rT2,rT0; /* 2: F = F' or F" */ \
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rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
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add d,d,rT2; /* 2: E = E + F */ \
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add d,d,rT0 /* 2: E = E + A' */
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#define R_60_79(a, b, c, d, e, w0, w1, w4, w6, w7, k) \
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R_20_39(a, b, c, d, e, w0, w1, w4, w6, w7, k)
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_GLOBAL(ppc_spe_sha1_transform)
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INITIALIZE
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lwz rH0,0(rHP)
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lwz rH1,4(rHP)
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mtctr r5
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lwz rH2,8(rHP)
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lis rKP,PPC_SPE_SHA1_K@h
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lwz rH3,12(rHP)
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ori rKP,rKP,PPC_SPE_SHA1_K@l
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lwz rH4,16(rHP)
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ppc_spe_sha1_main:
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R_00_15(rH0, rH1, rH2, rH3, rH4, rW1, rW0, 1, 0)
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R_00_15(rH3, rH4, rH0, rH1, rH2, rW2, rW1, 0, 8)
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R_00_15(rH1, rH2, rH3, rH4, rH0, rW3, rW2, 0, 16)
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R_00_15(rH4, rH0, rH1, rH2, rH3, rW4, rW3, 0, 24)
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R_00_15(rH2, rH3, rH4, rH0, rH1, rW5, rW4, 0, 32)
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R_00_15(rH0, rH1, rH2, rH3, rH4, rW6, rW5, 0, 40)
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R_00_15(rH3, rH4, rH0, rH1, rH2, rT3, rW6, 0, 48)
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R_00_15(rH1, rH2, rH3, rH4, rH0, rT3, rW7, 0, 56)
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R_16_19(rH4, rH0, rH1, rH2, rH3, rW0, rW1, rW4, rW6, rW7, 0)
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R_16_19(rH2, rH3, rH4, rH0, rH1, rW1, rW2, rW5, rW7, rW0, 2)
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R_20_39(rH0, rH1, rH2, rH3, rH4, rW2, rW3, rW6, rW0, rW1, 0)
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R_20_39(rH3, rH4, rH0, rH1, rH2, rW3, rW4, rW7, rW1, rW2, 0)
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R_20_39(rH1, rH2, rH3, rH4, rH0, rW4, rW5, rW0, rW2, rW3, 0)
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R_20_39(rH4, rH0, rH1, rH2, rH3, rW5, rW6, rW1, rW3, rW4, 0)
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R_20_39(rH2, rH3, rH4, rH0, rH1, rW6, rW7, rW2, rW4, rW5, 0)
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R_20_39(rH0, rH1, rH2, rH3, rH4, rW7, rW0, rW3, rW5, rW6, 0)
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R_20_39(rH3, rH4, rH0, rH1, rH2, rW0, rW1, rW4, rW6, rW7, 0)
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R_20_39(rH1, rH2, rH3, rH4, rH0, rW1, rW2, rW5, rW7, rW0, 0)
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R_20_39(rH4, rH0, rH1, rH2, rH3, rW2, rW3, rW6, rW0, rW1, 0)
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R_20_39(rH2, rH3, rH4, rH0, rH1, rW3, rW4, rW7, rW1, rW2, 3)
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R_40_59(rH0, rH1, rH2, rH3, rH4, rW4, rW5, rW0, rW2, rW3, 0)
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R_40_59(rH3, rH4, rH0, rH1, rH2, rW5, rW6, rW1, rW3, rW4, 0)
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R_40_59(rH1, rH2, rH3, rH4, rH0, rW6, rW7, rW2, rW4, rW5, 0)
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R_40_59(rH4, rH0, rH1, rH2, rH3, rW7, rW0, rW3, rW5, rW6, 0)
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R_40_59(rH2, rH3, rH4, rH0, rH1, rW0, rW1, rW4, rW6, rW7, 0)
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R_40_59(rH0, rH1, rH2, rH3, rH4, rW1, rW2, rW5, rW7, rW0, 0)
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R_40_59(rH3, rH4, rH0, rH1, rH2, rW2, rW3, rW6, rW0, rW1, 0)
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R_40_59(rH1, rH2, rH3, rH4, rH0, rW3, rW4, rW7, rW1, rW2, 0)
|
||
|
|
R_40_59(rH4, rH0, rH1, rH2, rH3, rW4, rW5, rW0, rW2, rW3, 0)
|
||
|
|
R_40_59(rH2, rH3, rH4, rH0, rH1, rW5, rW6, rW1, rW3, rW4, 4)
|
||
|
|
|
||
|
|
R_60_79(rH0, rH1, rH2, rH3, rH4, rW6, rW7, rW2, rW4, rW5, 0)
|
||
|
|
R_60_79(rH3, rH4, rH0, rH1, rH2, rW7, rW0, rW3, rW5, rW6, 0)
|
||
|
|
R_60_79(rH1, rH2, rH3, rH4, rH0, rW0, rW1, rW4, rW6, rW7, 0)
|
||
|
|
R_60_79(rH4, rH0, rH1, rH2, rH3, rW1, rW2, rW5, rW7, rW0, 0)
|
||
|
|
R_60_79(rH2, rH3, rH4, rH0, rH1, rW2, rW3, rW6, rW0, rW1, 0)
|
||
|
|
R_60_79(rH0, rH1, rH2, rH3, rH4, rW3, rW4, rW7, rW1, rW2, 0)
|
||
|
|
R_60_79(rH3, rH4, rH0, rH1, rH2, rW4, rW5, rW0, rW2, rW3, 0)
|
||
|
|
lwz rT3,0(rHP)
|
||
|
|
R_60_79(rH1, rH2, rH3, rH4, rH0, rW5, rW6, rW1, rW3, rW4, 0)
|
||
|
|
lwz rW1,4(rHP)
|
||
|
|
R_60_79(rH4, rH0, rH1, rH2, rH3, rW6, rW7, rW2, rW4, rW5, 0)
|
||
|
|
lwz rW2,8(rHP)
|
||
|
|
R_60_79(rH2, rH3, rH4, rH0, rH1, rW7, rW0, rW3, rW5, rW6, 0)
|
||
|
|
lwz rW3,12(rHP)
|
||
|
|
NEXT_BLOCK
|
||
|
|
lwz rW4,16(rHP)
|
||
|
|
|
||
|
|
add rH0,rH0,rT3
|
||
|
|
stw rH0,0(rHP)
|
||
|
|
add rH1,rH1,rW1
|
||
|
|
stw rH1,4(rHP)
|
||
|
|
add rH2,rH2,rW2
|
||
|
|
stw rH2,8(rHP)
|
||
|
|
add rH3,rH3,rW3
|
||
|
|
stw rH3,12(rHP)
|
||
|
|
add rH4,rH4,rW4
|
||
|
|
stw rH4,16(rHP)
|
||
|
|
|
||
|
|
bdnz ppc_spe_sha1_main
|
||
|
|
|
||
|
|
FINALIZE
|
||
|
|
blr
|
||
|
|
|
||
|
|
.data
|
||
|
|
.align 4
|
||
|
|
PPC_SPE_SHA1_K:
|
||
|
|
.long 0x5A827999,0x6ED9EBA1,0x8F1BBCDC,0xCA62C1D6
|