openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity
linux/drivers/i2c/busses/i2c-bcm2835.c

523 lines
13 KiB
C
Raw Normal View History

i2c: bcm2835: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-11-10 23:49:16 +08:00
// SPDX-License-Identifier: GPL-2.0
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
/*
* BCM2835 master mode driver
*/
#include <linux/clk.h>
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
i2c: bcm2835: Avoid clk stretch quirk for BCM2711 The I2C block on the BCM2711 isn't affected by the clk stretching bug. So there is no need to apply the corresponding quirk. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-28 01:04:15 +08:00
#include <linux/of_device.h>
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
#include <linux/platform_device.h>
#include <linux/slab.h>
#define BCM2835_I2C_C 0x0
#define BCM2835_I2C_S 0x4
#define BCM2835_I2C_DLEN 0x8
#define BCM2835_I2C_A 0xc
#define BCM2835_I2C_FIFO 0x10
#define BCM2835_I2C_DIV 0x14
#define BCM2835_I2C_DEL 0x18
#define BCM2835_I2C_CLKT 0x1c
#define BCM2835_I2C_C_READ BIT(0)
#define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */
#define BCM2835_I2C_C_ST BIT(7)
#define BCM2835_I2C_C_INTD BIT(8)
#define BCM2835_I2C_C_INTT BIT(9)
#define BCM2835_I2C_C_INTR BIT(10)
#define BCM2835_I2C_C_I2CEN BIT(15)
#define BCM2835_I2C_S_TA BIT(0)
#define BCM2835_I2C_S_DONE BIT(1)
#define BCM2835_I2C_S_TXW BIT(2)
#define BCM2835_I2C_S_RXR BIT(3)
#define BCM2835_I2C_S_TXD BIT(4)
#define BCM2835_I2C_S_RXD BIT(5)
#define BCM2835_I2C_S_TXE BIT(6)
#define BCM2835_I2C_S_RXF BIT(7)
#define BCM2835_I2C_S_ERR BIT(8)
#define BCM2835_I2C_S_CLKT BIT(9)
#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
i2c: bcm2835: Set up the rising/falling edge delays We were leaving them in the power on state (or the state the firmware had set up for some client, if we were taking over from them). The boot state was 30 core clocks, when we actually want to sample some time after (to make sure that the new input bit has actually arrived). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2018-02-08 21:54:05 +08:00
#define BCM2835_I2C_FEDL_SHIFT 16
#define BCM2835_I2C_REDL_SHIFT 0
i2c: busses: i2c-bcm2835: limits cdiv to allowed values Checks if the cdiv value is in between min (0x2) and max (0xFFFE) supported values by the bcm2835. If not, it returns -ENODEV. See page 33/34 of BCM2835-ARM-Peripherals.pdf for the DIV register. https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Signed-off-by: Silvan Wicki <linux_wi@tinag.ch> [wsa: resolved a merge conflict] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-06-18 17:10:11 +08:00
#define BCM2835_I2C_CDIV_MIN 0x0002
#define BCM2835_I2C_CDIV_MAX 0xFFFE
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
struct bcm2835_i2c_dev {
struct device *dev;
void __iomem *regs;
int irq;
struct i2c_adapter adapter;
struct completion completion;
i2c: bcm2835: Fix hang for writing messages larger than 16 bytes Writing messages larger than the FIFO size results in a hang, rendering the machine unusable. This is because the RXD status flag is set on the first interrupt which results in bcm2835_drain_rxfifo() stealing bytes from the buffer. The controller continues to trigger interrupts waiting for the missing bytes, but bcm2835_fill_txfifo() has none to give. In this situation wait_for_completion_timeout() apparently is unable to stop the madness. The BCM2835 ARM Peripherals datasheet has this to say about the flags: TXD: is set when the FIFO has space for at least one byte of data. RXD: is set when the FIFO contains at least one byte of data. TXW: is set during a write transfer and the FIFO is less than full. RXR: is set during a read transfer and the FIFO is or more full. Implementing the logic from the downstream i2c-bcm2708 driver solved the hang problem. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:08 +08:00
struct i2c_msg *curr_msg;
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
struct clk *bus_clk;
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
int num_msgs;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
u32 msg_err;
u8 *msg_buf;
size_t msg_buf_remaining;
};
static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
u32 reg, u32 val)
{
writel(val, i2c_dev->regs + reg);
}
static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
{
return readl(i2c_dev->regs + reg);
}
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
#define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
struct clk_bcm2835_i2c {
struct clk_hw hw;
struct bcm2835_i2c_dev *i2c_dev;
};
static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
unsigned long parent_rate)
i2c: bcm2835: Add support for dynamic clock Support a dynamic clock by reading the frequency and setting the divisor in the transfer function instead of during probe. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:14 +08:00
{
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
u32 divider = DIV_ROUND_UP(parent_rate, rate);
i2c: bcm2835: Add support for dynamic clock Support a dynamic clock by reading the frequency and setting the divisor in the transfer function instead of during probe. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:14 +08:00
/*
* Per the datasheet, the register is always interpreted as an even
* number, by rounding down. In other words, the LSB is ignored. So,
* if the LSB is set, increment the divider to avoid any issue.
*/
if (divider & 1)
divider++;
if ((divider < BCM2835_I2C_CDIV_MIN) ||
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
(divider > BCM2835_I2C_CDIV_MAX))
i2c: bcm2835: Add support for dynamic clock Support a dynamic clock by reading the frequency and setting the divisor in the transfer function instead of during probe. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:14 +08:00
return -EINVAL;
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
return divider;
}
static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
u32 redl, fedl;
u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
if (divider == -EINVAL)
return -EINVAL;
bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
i2c: bcm2835: Add support for dynamic clock Support a dynamic clock by reading the frequency and setting the divisor in the transfer function instead of during probe. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:14 +08:00
i2c: bcm2835: Set up the rising/falling edge delays We were leaving them in the power on state (or the state the firmware had set up for some client, if we were taking over from them). The boot state was 30 core clocks, when we actually want to sample some time after (to make sure that the new input bit has actually arrived). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2018-02-08 21:54:05 +08:00
/*
* Number of core clocks to wait after falling edge before
* outputting the next data bit. Note that both FEDL and REDL
* can't be greater than CDIV/2.
*/
fedl = max(divider / 16, 1u);
/*
* Number of core clocks to wait after rising edge before
* sampling the next incoming data bit.
*/
redl = max(divider / 4, 1u);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
i2c: bcm2835: Set up the rising/falling edge delays We were leaving them in the power on state (or the state the firmware had set up for some client, if we were taking over from them). The boot state was 30 core clocks, when we actually want to sample some time after (to make sure that the new input bit has actually arrived). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2018-02-08 21:54:05 +08:00
(fedl << BCM2835_I2C_FEDL_SHIFT) |
(redl << BCM2835_I2C_REDL_SHIFT));
i2c: bcm2835: Add support for dynamic clock Support a dynamic clock by reading the frequency and setting the divisor in the transfer function instead of during probe. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:14 +08:00
return 0;
}
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate);
return DIV_ROUND_UP(*parent_rate, divider);
}
static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
return DIV_ROUND_UP(parent_rate, divider);
}
static const struct clk_ops clk_bcm2835_i2c_ops = {
.set_rate = clk_bcm2835_i2c_set_rate,
.round_rate = clk_bcm2835_i2c_round_rate,
.recalc_rate = clk_bcm2835_i2c_recalc_rate,
};
static struct clk *bcm2835_i2c_register_div(struct device *dev,
i2c: bcm2835: Ensure clock exists when probing Probe function fails to recognize that upstream clock actually doesn't yet exist because clock driver has not been initialized. Actually try to go get the clock and test for its existence before trying to set up a downstream clock based upon it. This fixes a bug that causes the i2c driver not to work with monolithic kernels. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:50 +08:00
struct clk *mclk,
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
struct bcm2835_i2c_dev *i2c_dev)
{
struct clk_init_data init;
struct clk_bcm2835_i2c *priv;
char name[32];
i2c: bcm2835: Ensure clock exists when probing Probe function fails to recognize that upstream clock actually doesn't yet exist because clock driver has not been initialized. Actually try to go get the clock and test for its existence before trying to set up a downstream clock based upon it. This fixes a bug that causes the i2c driver not to work with monolithic kernels. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:50 +08:00
const char *mclk_name;
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
snprintf(name, sizeof(name), "%s_div", dev_name(dev));
i2c: bcm2835: Ensure clock exists when probing Probe function fails to recognize that upstream clock actually doesn't yet exist because clock driver has not been initialized. Actually try to go get the clock and test for its existence before trying to set up a downstream clock based upon it. This fixes a bug that causes the i2c driver not to work with monolithic kernels. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:50 +08:00
mclk_name = __clk_get_name(mclk);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
init.ops = &clk_bcm2835_i2c_ops;
init.name = name;
init.parent_names = (const char* []) { mclk_name };
init.num_parents = 1;
init.flags = 0;
priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
if (priv == NULL)
return ERR_PTR(-ENOMEM);
priv->hw.init = &init;
priv->i2c_dev = i2c_dev;
clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
return devm_clk_register(dev, &priv->hw);
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
{
u32 val;
while (i2c_dev->msg_buf_remaining) {
val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
if (!(val & BCM2835_I2C_S_TXD))
break;
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
*i2c_dev->msg_buf);
i2c_dev->msg_buf++;
i2c_dev->msg_buf_remaining--;
}
}
static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
{
u32 val;
while (i2c_dev->msg_buf_remaining) {
val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
if (!(val & BCM2835_I2C_S_RXD))
break;
*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
BCM2835_I2C_FIFO);
i2c_dev->msg_buf++;
i2c_dev->msg_buf_remaining--;
}
}
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
/*
* Repeated Start Condition (Sr)
* The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
* talks about reading from a slave with 10 bit address. This is achieved by
* issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
* issue a read.
* A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
* firmware actually does it using polling and says that it's a workaround for
* a problem in the state machine.
* It turns out that it is possible to use the TXW interrupt to know when the
* transfer is active, provided the FIFO has not been prefilled.
*/
static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
{
u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
struct i2c_msg *msg = i2c_dev->curr_msg;
bool last_msg = (i2c_dev->num_msgs == 1);
if (!i2c_dev->num_msgs)
return;
i2c_dev->num_msgs--;
i2c_dev->msg_buf = msg->buf;
i2c_dev->msg_buf_remaining = msg->len;
if (msg->flags & I2C_M_RD)
c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
else
c |= BCM2835_I2C_C_INTT;
if (last_msg)
c |= BCM2835_I2C_C_INTD;
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
}
i2c: bcm2835: Clear current buffer pointers and counts after a transfer The driver's interrupt handler checks whether a message is currently being handled with the curr_msg pointer. When it is NULL, the interrupt is considered to be unexpected. Similarly, the i2c_start_transfer routine checks for the remaining number of messages to handle in num_msgs. However, these values are never cleared and always keep the message and number relevant to the latest transfer (which might be done already and the underlying message memory might have been freed). When an unexpected interrupt hits with the DONE bit set, the isr will then try to access the flags field of the curr_msg structure, leading to a fatal page fault. The msg_buf and msg_buf_remaining fields are also never cleared at the end of the transfer, which can lead to similar pitfalls. Fix these issues by introducing a cleanup function and always calling it after a transfer is finished. Fixes: e2474541032d ("i2c: bcm2835: Fix hang for writing messages larger than 16 bytes") Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-27 23:42:25 +08:00
static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
{
i2c_dev->curr_msg = NULL;
i2c_dev->num_msgs = 0;
i2c_dev->msg_buf = NULL;
i2c_dev->msg_buf_remaining = 0;
}
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
/*
* Note about I2C_C_CLEAR on error:
* The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
* non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
* the state machine to send a NACK and a STOP. Since we're setting CLEAR
* without I2CEN, that NACK will be hanging around queued up for next time
* we start the engine.
*/
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
{
struct bcm2835_i2c_dev *i2c_dev = data;
u32 val, err;
val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
if (err) {
i2c_dev->msg_err = err;
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
goto complete;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
}
if (val & BCM2835_I2C_S_DONE) {
i2c: bcm2835: Avoid possible NULL ptr dereference Since commit e2474541032d ("bcm2835: Fix hang for writing messages larger than 16 bytes") the interrupt handler is prone to a possible NULL pointer dereference. This could happen if an interrupt fires before curr_msg is set by bcm2835_i2c_xfer_msg() and randomly occurs on the RPi 3. Even this is an unexpected behavior the driver must handle that with an error instead of a crash. Reported-by: Peter Robinson <pbrobinson@gmail.com> Fixes: e2474541032d ("bcm2835: Fix hang for writing messages larger than 16 bytes") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-02-17 05:20:45 +08:00
if (!i2c_dev->curr_msg) {
dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
i2c: bcm2835: Fix hang for writing messages larger than 16 bytes Writing messages larger than the FIFO size results in a hang, rendering the machine unusable. This is because the RXD status flag is set on the first interrupt which results in bcm2835_drain_rxfifo() stealing bytes from the buffer. The controller continues to trigger interrupts waiting for the missing bytes, but bcm2835_fill_txfifo() has none to give. In this situation wait_for_completion_timeout() apparently is unable to stop the madness. The BCM2835 ARM Peripherals datasheet has this to say about the flags: TXD: is set when the FIFO has space for at least one byte of data. RXD: is set when the FIFO contains at least one byte of data. TXW: is set during a write transfer and the FIFO is less than full. RXR: is set during a read transfer and the FIFO is or more full. Implementing the logic from the downstream i2c-bcm2708 driver solved the hang problem. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:08 +08:00
bcm2835_drain_rxfifo(i2c_dev);
val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
}
if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c_dev->msg_err = BCM2835_I2C_S_LEN;
else
i2c_dev->msg_err = 0;
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
goto complete;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
}
i2c: bcm2835: Fix hang for writing messages larger than 16 bytes Writing messages larger than the FIFO size results in a hang, rendering the machine unusable. This is because the RXD status flag is set on the first interrupt which results in bcm2835_drain_rxfifo() stealing bytes from the buffer. The controller continues to trigger interrupts waiting for the missing bytes, but bcm2835_fill_txfifo() has none to give. In this situation wait_for_completion_timeout() apparently is unable to stop the madness. The BCM2835 ARM Peripherals datasheet has this to say about the flags: TXD: is set when the FIFO has space for at least one byte of data. RXD: is set when the FIFO contains at least one byte of data. TXW: is set during a write transfer and the FIFO is less than full. RXR: is set during a read transfer and the FIFO is or more full. Implementing the logic from the downstream i2c-bcm2708 driver solved the hang problem. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:08 +08:00
if (val & BCM2835_I2C_S_TXW) {
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
if (!i2c_dev->msg_buf_remaining) {
i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
goto complete;
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
bcm2835_fill_txfifo(i2c_dev);
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
i2c_dev->curr_msg++;
bcm2835_i2c_start_transfer(i2c_dev);
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
return IRQ_HANDLED;
}
i2c: bcm2835: Fix hang for writing messages larger than 16 bytes Writing messages larger than the FIFO size results in a hang, rendering the machine unusable. This is because the RXD status flag is set on the first interrupt which results in bcm2835_drain_rxfifo() stealing bytes from the buffer. The controller continues to trigger interrupts waiting for the missing bytes, but bcm2835_fill_txfifo() has none to give. In this situation wait_for_completion_timeout() apparently is unable to stop the madness. The BCM2835 ARM Peripherals datasheet has this to say about the flags: TXD: is set when the FIFO has space for at least one byte of data. RXD: is set when the FIFO contains at least one byte of data. TXW: is set during a write transfer and the FIFO is less than full. RXR: is set during a read transfer and the FIFO is or more full. Implementing the logic from the downstream i2c-bcm2708 driver solved the hang problem. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:08 +08:00
if (val & BCM2835_I2C_S_RXR) {
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
if (!i2c_dev->msg_buf_remaining) {
i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
goto complete;
}
i2c: bcm2835: Fix hang for writing messages larger than 16 bytes Writing messages larger than the FIFO size results in a hang, rendering the machine unusable. This is because the RXD status flag is set on the first interrupt which results in bcm2835_drain_rxfifo() stealing bytes from the buffer. The controller continues to trigger interrupts waiting for the missing bytes, but bcm2835_fill_txfifo() has none to give. In this situation wait_for_completion_timeout() apparently is unable to stop the madness. The BCM2835 ARM Peripherals datasheet has this to say about the flags: TXD: is set when the FIFO has space for at least one byte of data. RXD: is set when the FIFO contains at least one byte of data. TXW: is set during a write transfer and the FIFO is less than full. RXR: is set during a read transfer and the FIFO is or more full. Implementing the logic from the downstream i2c-bcm2708 driver solved the hang problem. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:08 +08:00
bcm2835_drain_rxfifo(i2c_dev);
return IRQ_HANDLED;
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
return IRQ_NONE;
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
complete:
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
complete(&i2c_dev->completion);
return IRQ_HANDLED;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
}
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
int num)
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
{
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
i2c: i2c-bcm2835: match return type of wait_for_completion_timeout return type of wait_for_completion_timeout is unsigned long not int. as time_left is used for wait_for_completion_timeout exclusively here its type is simply changed to unsigned long. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-02-08 19:04:18 +08:00
unsigned long time_left;
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
int i;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
for (i = 0; i < (num - 1); i++)
if (msgs[i].flags & I2C_M_RD) {
dev_warn_once(i2c_dev->dev,
"only one read message supported, has to be last\n");
return -EOPNOTSUPP;
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
i2c_dev->curr_msg = msgs;
i2c_dev->num_msgs = num;
reinit_completion(&i2c_dev->completion);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
bcm2835_i2c_start_transfer(i2c_dev);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
time_left = wait_for_completion_timeout(&i2c_dev->completion,
i2c: bcm2835: Support i2c-dev ioctl I2C_TIMEOUT Use i2c_adapter->timeout for the completion timeout value. The core default is 1 second. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:13 +08:00
adap->timeout);
i2c: bcm2835: Clear current buffer pointers and counts after a transfer The driver's interrupt handler checks whether a message is currently being handled with the curr_msg pointer. When it is NULL, the interrupt is considered to be unexpected. Similarly, the i2c_start_transfer routine checks for the remaining number of messages to handle in num_msgs. However, these values are never cleared and always keep the message and number relevant to the latest transfer (which might be done already and the underlying message memory might have been freed). When an unexpected interrupt hits with the DONE bit set, the isr will then try to access the flags field of the curr_msg structure, leading to a fatal page fault. The msg_buf and msg_buf_remaining fields are also never cleared at the end of the transfer, which can lead to similar pitfalls. Fix these issues by introducing a cleanup function and always calling it after a transfer is finished. Fixes: e2474541032d ("i2c: bcm2835: Fix hang for writing messages larger than 16 bytes") Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-27 23:42:25 +08:00
bcm2835_i2c_finish_transfer(i2c_dev);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
if (!time_left) {
i2c: bcm2835: Protect against unexpected TXW/RXR interrupts If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0), the driver has no way to fill/drain the FIFO to stop the interrupts. In this case the controller has to be disabled and the transfer completed to avoid hang. (CLKT | ERR) and DONE interrupts are completed in their own paths, and the controller is disabled in the transfer function after completion. Unite the code paths and do disabling inside the interrupt routine. Clear interrupt status bits in the united completion path instead of trying to do it on every interrupt which isn't necessary. Only CLKT, ERR and DONE can be cleared that way. Add the status value to the error value in case of TXW/RXR errors to distinguish them from the other S_LEN error. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:09 +08:00
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
BCM2835_I2C_C_CLEAR);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
dev_err(i2c_dev->dev, "i2c transfer timed out\n");
return -ETIMEDOUT;
}
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
if (!i2c_dev->msg_err)
return num;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c: bcm2835: Use dev_dbg logging on transfer errors Writing to an AT24C32 generates on average 2x i2c transfer errors per 32-byte page write. Which amounts to a lot for a 4k write. This is due to the fact that the chip doesn't respond during it's internal write cycle when the at24 driver tries and retries the next write. Only a handful drivers use dev_err() on transfer error, so switch to dev_dbg() instead. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:10 +08:00
dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
return -EREMOTEIO;
i2c: bcm2835: Add support for Repeated Start Condition Documentation/i2c/i2c-protocol states that Combined transactions should separate messages with a Start bit and end the whole transaction with a Stop bit. This patch adds support for issuing only a Start between messages instead of a Stop followed by a Start. This implementation differs from downstream i2c-bcm2708 in 2 respects: - it uses an interrupt to detect that the transfer is active instead of using polling. There is no interrupt for Transfer Active, but by not prefilling the FIFO it's possible to use the TXW interrupt. - when resetting/disabling the controller between transfers it writes CLEAR to the control register instead of just zero. Using just zero gave many errors. This might be the reason why downstream had to disable this feature and make it available with a module parameter. I have run thousands of transfers to a DS1307 (rtc), MMA8451 (accel) and AT24C32 (eeprom) in parallel without problems. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-10-04 04:06:12 +08:00
return -EIO;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
}
static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm bcm2835_i2c_algo = {
.master_xfer = bcm2835_i2c_xfer,
.functionality = bcm2835_i2c_func,
};
i2c: bcm2835: add I2C_AQ_NO_CLK_STRETCH As reported in the links given below. the BCM2835 has a hardware bug in its i2c module which prevents a correct clock stretching. This patch adds the I2C_AQ_NO_CLK_STRETCH quirk flag to i2c-bcm2835. Signed-off-by: Nicola Corna <nicola@corna.info> [wsa: put the links into the code as comments] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-10-29 19:34:25 +08:00
/*
i2c: bcm2835: Avoid clk stretch quirk for BCM2711 The I2C block on the BCM2711 isn't affected by the clk stretching bug. So there is no need to apply the corresponding quirk. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-28 01:04:15 +08:00
* The BCM2835 was reported to have problems with clock stretching:
i2c: bcm2835: Replace HTTP links with HTTPS ones Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> [wsa: shortened commit message] Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-07-18 02:52:47 +08:00
* https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
i2c: bcm2835: add I2C_AQ_NO_CLK_STRETCH As reported in the links given below. the BCM2835 has a hardware bug in its i2c module which prevents a correct clock stretching. This patch adds the I2C_AQ_NO_CLK_STRETCH quirk flag to i2c-bcm2835. Signed-off-by: Nicola Corna <nicola@corna.info> [wsa: put the links into the code as comments] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-10-29 19:34:25 +08:00
* https://www.raspberrypi.org/forums/viewtopic.php?p=146272
*/
static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
.flags = I2C_AQ_NO_CLK_STRETCH,
};
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
static int bcm2835_i2c_probe(struct platform_device *pdev)
{
struct bcm2835_i2c_dev *i2c_dev;
i2c: bcm2835: Use devm_ioremap_resource() Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because the value is checked by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-02-11 21:02:36 +08:00
struct resource *mem, *irq;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
int ret;
struct i2c_adapter *adap;
i2c: bcm2835: Ensure clock exists when probing Probe function fails to recognize that upstream clock actually doesn't yet exist because clock driver has not been initialized. Actually try to go get the clock and test for its existence before trying to set up a downstream clock based upon it. This fixes a bug that causes the i2c driver not to work with monolithic kernels. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:50 +08:00
struct clk *mclk;
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
u32 bus_clk_rate;
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
i2c: remove unnecessary OOM messages The site-specific OOM messages are unnecessary, because they duplicate the MM subsystem generic OOM message. For example, k.alloc and v.alloc failures use dump_stack(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Felipe Balbi <balbi@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-05-13 09:51:58 +08:00
if (!i2c_dev)
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
return -ENOMEM;
platform_set_drvdata(pdev, i2c_dev);
i2c_dev->dev = &pdev->dev;
init_completion(&i2c_dev->completion);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
i2c: bcm2835: Use devm_ioremap_resource() Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because the value is checked by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-02-11 21:02:36 +08:00
i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(i2c_dev->regs))
return PTR_ERR(i2c_dev->regs);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
i2c: bcm2835: Ensure clock exists when probing Probe function fails to recognize that upstream clock actually doesn't yet exist because clock driver has not been initialized. Actually try to go get the clock and test for its existence before trying to set up a downstream clock based upon it. This fixes a bug that causes the i2c driver not to work with monolithic kernels. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:50 +08:00
mclk = devm_clk_get(&pdev->dev, NULL);
i2c: bcm2835: Simplify with dev_err_probe() Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2020-09-02 23:06:37 +08:00
if (IS_ERR(mclk))
return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
"Could not get clock\n");
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
if (IS_ERR(i2c_dev->bus_clk)) {
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
dev_err(&pdev->dev, "Could not register clock\n");
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
return PTR_ERR(i2c_dev->bus_clk);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
}
ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
&bus_clk_rate);
if (ret < 0) {
dev_warn(&pdev->dev,
"Could not read clock-frequency property\n");
i2c: drivers: Use generic definitions for bus frequencies Since we have generic definitions for bus frequencies, let's use them. Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Robert Richter <rrichter@marvell.com> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com> Acked-by: Elie Morisse <syniurge@gmail.com> Acked-by: Nehal Shah <nehal-bakulchandra.shah@amd.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Reviewed-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-03-24 20:32:16 +08:00
bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
}
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
if (ret < 0) {
dev_err(&pdev->dev, "Could not set clock frequency\n");
return ret;
}
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
ret = clk_prepare_enable(i2c_dev->bus_clk);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
if (ret) {
dev_err(&pdev->dev, "Couldn't prepare clock");
return ret;
}
i2c: bcm2835: Move IRQ request after clock code in probe If any of the clock code in the probe fails and returns, the IRQ will not be freed. Moving the IRQ request to last allows it to be freed on any errors further up in the probe function. devm_ calls can apparently not be used because there are some potential race conditions that will arise. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-21 18:52:49 +08:00
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!irq) {
dev_err(&pdev->dev, "No IRQ resource\n");
return -ENODEV;
}
i2c_dev->irq = irq->start;
ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
dev_name(&pdev->dev), i2c_dev);
if (ret) {
dev_err(&pdev->dev, "Could not request IRQ\n");
return -ENODEV;
}
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
adap = &i2c_dev->adapter;
i2c_set_adapdata(adap, i2c_dev);
adap->owner = THIS_MODULE;
i2c: i2c-bcm2835: Drop class based scanning to improve bootup time This driver has been flagged to drop class based instantiation. The removal improves boot-up time and is unneeded for embedded controllers. Users have been warned to switch for some time now, so we can actually do the removal. Keep the DEPRECATED flag, so the core can inform users that the behaviour finally changed now. After another transition period, this flag can go, too. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-07-10 19:46:23 +08:00
adap->class = I2C_CLASS_DEPRECATED;
i2c: bcm2835: Add full name of devicetree node to adapter name Inspired by Lori Hikichi's patch for iproc, this adds the full name of the devicetree node to the adapter name. With the introduction of BCM2711 it's very difficult to distinguish between the multiple instances. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-28 01:04:16 +08:00
snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
of_node_full_name(pdev->dev.of_node));
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
adap->algo = &bcm2835_i2c_algo;
adap->dev.parent = &pdev->dev;
i2c: bcm2835: Linking platform nodes to adapter nodes In order to find I2C devices in the device tree, the platform nodes have to be known by the I2C core. This requires setting the dev.of_node parameter of the adapter. Signed-off-by: Florian Meier <florian.meier@koalo.de> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2013-11-25 16:01:50 +08:00
adap->dev.of_node = pdev->dev.of_node;
i2c: bcm2835: Avoid clk stretch quirk for BCM2711 The I2C block on the BCM2711 isn't affected by the clk stretching bug. So there is no need to apply the corresponding quirk. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-28 01:04:15 +08:00
adap->quirks = of_device_get_match_data(&pdev->dev);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
ret = i2c_add_adapter(adap);
if (ret)
free_irq(i2c_dev->irq, i2c_dev);
return ret;
}
static int bcm2835_i2c_remove(struct platform_device *pdev)
{
struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
i2c: bcm2835: Model Divider in CCF Model the I2C bus clock divider as a part of the Core Clock Framework. Primarily this removes the clk_get_rate() call from each transfer. This call causes problems for slave drivers that themselves have internal clock components that are controlled by an I2C interface. When the slave's internal clock component is prepared, the prepare lock is obtained, and it makes calls to the I2C subsystem to command the hardware to activate the clock. In order to perform the I2C transfer, this driver sets the divider, which requires it to get the parent clock rate, which it does with clk_get_rate(). Unfortunately, this function will try to take the clock prepare lock, which is already held by the slave's internal clock calls creating a deadlock. Modeling the divider in the CCF natively removes this dependency and the divider value is only set upon changing the bus clock frequency or changes in the parent clock that cascade down to this divisor. This obviates the need to set the divider with every transfer and avoids the deadlock described above. It also should provide better clock debugging and save a few cycles on each transfer due to not having to recalcuate the divider value. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-09 01:14:43 +08:00
i2c: bcm2835: Store pointer to bus clock The commit bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") introduced a NULL pointer dereference on driver unload. It seems that we can't fetch the bus clock via devm_clk_get in bcm2835_i2c_remove. As an alternative approach store a pointer to the bus clock in the private driver structure. Fixes: bebff81fb8b9 ("i2c: bcm2835: Model Divider in CCF") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-04 23:13:20 +08:00
clk_rate_exclusive_put(i2c_dev->bus_clk);
clk_disable_unprepare(i2c_dev->bus_clk);
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
free_irq(i2c_dev->irq, i2c_dev);
i2c_del_adapter(&i2c_dev->adapter);
return 0;
}
static const struct of_device_id bcm2835_i2c_of_match[] = {
i2c: bcm2835: Avoid clk stretch quirk for BCM2711 The I2C block on the BCM2711 isn't affected by the clk stretching bug. So there is no need to apply the corresponding quirk. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-28 01:04:15 +08:00
{ .compatible = "brcm,bcm2711-i2c" },
{ .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
i2c: add bcm2835 driver This implements a very basic I2C host driver for the BCM2835 SoC. Missing features so far are: * 10-bit addressing. * DMA. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
2013-02-12 10:47:56 +08:00
{},
};
MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
static struct platform_driver bcm2835_i2c_driver = {
.probe = bcm2835_i2c_probe,
.remove = bcm2835_i2c_remove,
.driver = {
.name = "i2c-bcm2835",
.of_match_table = bcm2835_i2c_of_match,
},
};
module_platform_driver(bcm2835_i2c_driver);
MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:i2c-bcm2835");