mirror of https://gitee.com/openkylin/linux.git
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
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/*
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* Blackfin CPLB initialization
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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struct cplb_entry icplb_tbl[MAX_CPLBS];
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struct cplb_entry dcplb_tbl[MAX_CPLBS];
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int first_switched_icplb, first_switched_dcplb;
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int first_mask_dcplb;
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void __init generate_cpl_tables(void)
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{
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int i_d, i_i;
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unsigned long addr;
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unsigned long d_data, i_data;
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unsigned long d_cache = 0, i_cache = 0;
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#ifdef CONFIG_BFIN_ICACHE
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i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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d_cache = CPLB_L1_CHBL;
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#ifdef CONFIG_BLKFIN_WT
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d_cache |= CPLB_L1_AOW | CPLB_WT;
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#endif
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#endif
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i_d = i_i = 0;
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/* Set up the zero page. */
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dcplb_tbl[i_d].addr = 0;
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dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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#if 0
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icplb_tbl[i_i].addr = 0;
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icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
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#endif
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
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i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
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for (; addr < memory_start; addr += 4 * 1024 * 1024) {
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dcplb_tbl[i_d].addr = addr;
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dcplb_tbl[i_d++].data = d_data;
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icplb_tbl[i_i].addr = addr;
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icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
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}
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
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dcplb_tbl[i_d].addr = L1_DATA_A_START;
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dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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#endif
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icplb_tbl[i_i].addr = L1_CODE_START;
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icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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first_mask_dcplb = i_d;
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first_switched_dcplb = i_d + (1 << page_mask_order);
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first_switched_icplb = i_i;
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while (i_d < MAX_CPLBS)
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dcplb_tbl[i_d++].data = 0;
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while (i_i < MAX_CPLBS)
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icplb_tbl[i_i++].data = 0;
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}
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