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61 lines
2.0 KiB
Plaintext
61 lines
2.0 KiB
Plaintext
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STMicroelectronics STM32 Peripheral Reset Clock Controller
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==========================================================
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The RCC IP is both a reset and a clock controller.
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RCC makes also power management (resume/supend and wakeup interrupt).
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Please also refer to reset.txt for common reset controller binding usage.
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Please also refer to clock-bindings.txt for common clock controller
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binding usage.
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Required properties:
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- compatible: "st,stm32mp1-rcc", "syscon"
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- reg: should be register base and length as documented in the datasheet
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- #clock-cells: 1, device nodes should specify the clock in their
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"clocks" property, containing a phandle to the clock device node,
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an index specifying the clock to use.
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- #reset-cells: Shall be 1
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- interrupts: Should contain a general interrupt line and a interrupt line
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to the wake-up of processor (CSTOP).
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Example:
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
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<GIC_SPI 145 IRQ_TYPE_NONE>;
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};
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Specifying clocks
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=================
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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tree sources.
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Specifying softreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the reset device node and an index specifying
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which channel to use.
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The index is the bit number within the RCC registers bank, starting from RCC
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base address.
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register.
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For example on STM32MP1, for LTDC reset:
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ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
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= 0x180 / 4 * 32 + 0 = 3072
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The list of valid indices for STM32MP1 is available in:
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include/dt-bindings/reset-controller/stm32mp1-resets.h
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This file implements defines like:
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#define LTDC_R 3072
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