License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
|
2005-04-17 06:20:36 +08:00
|
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#ifndef _ASM_IA64_BITOPS_H
|
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|
|
#define _ASM_IA64_BITOPS_H
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|
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/*
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|
|
|
* Copyright (C) 1998-2003 Hewlett-Packard Co
|
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|
|
* David Mosberger-Tang <davidm@hpl.hp.com>
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*
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
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* 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
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* O(1) scheduler patch
|
2005-04-17 06:20:36 +08:00
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*/
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|
2007-10-19 14:40:26 +08:00
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#ifndef _LINUX_BITOPS_H
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|
#error only <linux/bitops.h> can be included directly
|
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#endif
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|
2005-04-17 06:20:36 +08:00
|
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|
#include <linux/compiler.h>
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|
#include <linux/types.h>
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|
#include <asm/intrinsics.h>
|
2014-03-14 02:00:36 +08:00
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#include <asm/barrier.h>
|
2005-04-17 06:20:36 +08:00
|
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|
|
/**
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|
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|
* set_bit - Atomically set a bit in memory
|
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|
* @nr: the bit to set
|
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|
|
* @addr: the address to start counting from
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|
*
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|
|
* This function is atomic and may not be reordered. See __set_bit()
|
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|
|
* if you do not require the atomic guarantees.
|
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|
|
* Note that @nr may be almost arbitrarily large; this function is not
|
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|
|
* restricted to acting on a single-word quantity.
|
|
|
|
*
|
|
|
|
* The address must be (at least) "long" aligned.
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
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* Note that there are driver (e.g., eepro100) which use these operations to
|
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|
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* operate on hw-defined data-structures, so we can't easily change these
|
|
|
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* operations to force a bigger alignment.
|
2005-04-17 06:20:36 +08:00
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|
*
|
|
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|
* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
|
|
|
|
*/
|
|
|
|
static __inline__ void
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|
set_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
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|
__u32 bit, old, new;
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|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
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|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
|
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|
bit = 1 << (nr & 31);
|
|
|
|
do {
|
|
|
|
CMPXCHG_BUGCHECK(m);
|
|
|
|
old = *m;
|
|
|
|
new = old | bit;
|
|
|
|
} while (cmpxchg_acq(m, old, new) != old);
|
|
|
|
}
|
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|
|
|
|
/**
|
|
|
|
* __set_bit - Set a bit in memory
|
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* @nr: the bit to set
|
|
|
|
* @addr: the address to start counting from
|
|
|
|
*
|
|
|
|
* Unlike set_bit(), this function is non-atomic and may be reordered.
|
|
|
|
* If it's called on the same region of memory simultaneously, the effect
|
|
|
|
* may be that only one operation succeeds.
|
|
|
|
*/
|
|
|
|
static __inline__ void
|
|
|
|
__set_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
*((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
|
|
|
|
}
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|
|
/**
|
|
|
|
* clear_bit - Clears a bit in memory
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|
* @nr: Bit to clear
|
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|
* @addr: Address to start counting from
|
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|
*
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|
|
|
* clear_bit() is atomic and may not be reordered. However, it does
|
|
|
|
* not contain a memory barrier, so if it is used for locking purposes,
|
2014-03-14 02:00:36 +08:00
|
|
|
* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
|
2005-04-17 06:20:36 +08:00
|
|
|
* in order to ensure changes are visible on other processors.
|
|
|
|
*/
|
|
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|
static __inline__ void
|
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|
clear_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 mask, old, new;
|
|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
|
|
|
|
|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
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mask = ~(1 << (nr & 31));
|
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|
do {
|
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CMPXCHG_BUGCHECK(m);
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|
old = *m;
|
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new = old & mask;
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|
} while (cmpxchg_acq(m, old, new) != old);
|
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}
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|
2007-10-18 18:06:52 +08:00
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|
/**
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* clear_bit_unlock - Clears a bit in memory with release
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit_unlock() is atomic and may not be reordered. It does
|
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* contain a memory barrier suitable for unlock type operations.
|
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*/
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static __inline__ void
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|
clear_bit_unlock (int nr, volatile void *addr)
|
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|
{
|
|
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|
__u32 mask, old, new;
|
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|
volatile __u32 *m;
|
|
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|
CMPXCHG_BUGCHECK_DECL
|
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m = (volatile __u32 *) addr + (nr >> 5);
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mask = ~(1 << (nr & 31));
|
|
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|
do {
|
|
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|
CMPXCHG_BUGCHECK(m);
|
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|
old = *m;
|
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|
new = old & mask;
|
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|
} while (cmpxchg_rel(m, old, new) != old);
|
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|
}
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|
/**
|
2008-02-05 07:19:16 +08:00
|
|
|
* __clear_bit_unlock - Non-atomically clears a bit in memory with release
|
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|
* @nr: Bit to clear
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|
* @addr: Address to start counting from
|
2007-10-18 18:06:52 +08:00
|
|
|
*
|
2008-02-05 07:19:16 +08:00
|
|
|
* Similarly to clear_bit_unlock, the implementation uses a store
|
2009-12-03 03:01:25 +08:00
|
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|
* with release semantics. See also arch_spin_unlock().
|
2007-10-18 18:06:52 +08:00
|
|
|
*/
|
2007-12-19 08:22:46 +08:00
|
|
|
static __inline__ void
|
2008-02-05 07:19:16 +08:00
|
|
|
__clear_bit_unlock(int nr, void *addr)
|
2007-12-19 08:22:46 +08:00
|
|
|
{
|
2008-02-05 07:19:16 +08:00
|
|
|
__u32 * const m = (__u32 *) addr + (nr >> 5);
|
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|
__u32 const new = *m & ~(1 << (nr & 31));
|
2007-12-19 08:22:46 +08:00
|
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ia64_st4_rel_nta(m, new);
|
|
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|
}
|
2007-10-18 18:06:52 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
|
|
|
* __clear_bit - Clears a bit in memory (non-atomic version)
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: the bit to clear
|
|
|
|
* @addr: the address to start counting from
|
|
|
|
*
|
|
|
|
* Unlike clear_bit(), this function is non-atomic and may be reordered.
|
|
|
|
* If it's called on the same region of memory simultaneously, the effect
|
|
|
|
* may be that only one operation succeeds.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static __inline__ void
|
|
|
|
__clear_bit (int nr, volatile void *addr)
|
|
|
|
{
|
2008-02-05 07:19:16 +08:00
|
|
|
*((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
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|
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|
|
/**
|
|
|
|
* change_bit - Toggle a bit in memory
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: Bit to toggle
|
2005-04-17 06:20:36 +08:00
|
|
|
* @addr: Address to start counting from
|
|
|
|
*
|
|
|
|
* change_bit() is atomic and may not be reordered.
|
|
|
|
* Note that @nr may be almost arbitrarily large; this function is not
|
|
|
|
* restricted to acting on a single-word quantity.
|
|
|
|
*/
|
|
|
|
static __inline__ void
|
|
|
|
change_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 bit, old, new;
|
|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
|
|
|
|
|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
|
|
|
bit = (1 << (nr & 31));
|
|
|
|
do {
|
|
|
|
CMPXCHG_BUGCHECK(m);
|
|
|
|
old = *m;
|
|
|
|
new = old ^ bit;
|
|
|
|
} while (cmpxchg_acq(m, old, new) != old);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __change_bit - Toggle a bit in memory
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: the bit to toggle
|
2005-04-17 06:20:36 +08:00
|
|
|
* @addr: the address to start counting from
|
|
|
|
*
|
|
|
|
* Unlike change_bit(), this function is non-atomic and may be reordered.
|
|
|
|
* If it's called on the same region of memory simultaneously, the effect
|
|
|
|
* may be that only one operation succeeds.
|
|
|
|
*/
|
|
|
|
static __inline__ void
|
|
|
|
__change_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
*((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* test_and_set_bit - Set a bit and return its old value
|
|
|
|
* @nr: Bit to set
|
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is atomic and cannot be reordered.
|
2008-02-05 07:19:16 +08:00
|
|
|
* It also implies the acquisition side of the memory barrier.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
test_and_set_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 bit, old, new;
|
|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
|
|
|
|
|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
|
|
|
bit = 1 << (nr & 31);
|
|
|
|
do {
|
|
|
|
CMPXCHG_BUGCHECK(m);
|
|
|
|
old = *m;
|
|
|
|
new = old | bit;
|
|
|
|
} while (cmpxchg_acq(m, old, new) != old);
|
|
|
|
return (old & bit) != 0;
|
|
|
|
}
|
|
|
|
|
2007-10-18 18:06:52 +08:00
|
|
|
/**
|
|
|
|
* test_and_set_bit_lock - Set a bit and return its old value for lock
|
|
|
|
* @nr: Bit to set
|
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This is the same as test_and_set_bit on ia64
|
|
|
|
*/
|
|
|
|
#define test_and_set_bit_lock test_and_set_bit
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
|
|
|
* __test_and_set_bit - Set a bit and return its old value
|
|
|
|
* @nr: Bit to set
|
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is non-atomic and can be reordered.
|
|
|
|
* If two examples of this operation race, one can appear to succeed
|
|
|
|
* but actually fail. You must protect multiple accesses with a lock.
|
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
__test_and_set_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 *p = (__u32 *) addr + (nr >> 5);
|
|
|
|
__u32 m = 1 << (nr & 31);
|
|
|
|
int oldbitset = (*p & m) != 0;
|
|
|
|
|
|
|
|
*p |= m;
|
|
|
|
return oldbitset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* test_and_clear_bit - Clear a bit and return its old value
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: Bit to clear
|
2005-04-17 06:20:36 +08:00
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is atomic and cannot be reordered.
|
2008-02-05 07:19:16 +08:00
|
|
|
* It also implies the acquisition side of the memory barrier.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
test_and_clear_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 mask, old, new;
|
|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
|
|
|
|
|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
|
|
|
mask = ~(1 << (nr & 31));
|
|
|
|
do {
|
|
|
|
CMPXCHG_BUGCHECK(m);
|
|
|
|
old = *m;
|
|
|
|
new = old & mask;
|
|
|
|
} while (cmpxchg_acq(m, old, new) != old);
|
|
|
|
return (old & ~mask) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __test_and_clear_bit - Clear a bit and return its old value
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: Bit to clear
|
2005-04-17 06:20:36 +08:00
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is non-atomic and can be reordered.
|
|
|
|
* If two examples of this operation race, one can appear to succeed
|
|
|
|
* but actually fail. You must protect multiple accesses with a lock.
|
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
__test_and_clear_bit(int nr, volatile void * addr)
|
|
|
|
{
|
|
|
|
__u32 *p = (__u32 *) addr + (nr >> 5);
|
|
|
|
__u32 m = 1 << (nr & 31);
|
2009-08-12 05:52:10 +08:00
|
|
|
int oldbitset = (*p & m) != 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
*p &= ~m;
|
|
|
|
return oldbitset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* test_and_change_bit - Change a bit and return its old value
|
2008-02-05 07:19:16 +08:00
|
|
|
* @nr: Bit to change
|
2005-04-17 06:20:36 +08:00
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is atomic and cannot be reordered.
|
2008-02-05 07:19:16 +08:00
|
|
|
* It also implies the acquisition side of the memory barrier.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
test_and_change_bit (int nr, volatile void *addr)
|
|
|
|
{
|
|
|
|
__u32 bit, old, new;
|
|
|
|
volatile __u32 *m;
|
|
|
|
CMPXCHG_BUGCHECK_DECL
|
|
|
|
|
|
|
|
m = (volatile __u32 *) addr + (nr >> 5);
|
|
|
|
bit = (1 << (nr & 31));
|
|
|
|
do {
|
|
|
|
CMPXCHG_BUGCHECK(m);
|
|
|
|
old = *m;
|
|
|
|
new = old ^ bit;
|
|
|
|
} while (cmpxchg_acq(m, old, new) != old);
|
|
|
|
return (old & bit) != 0;
|
|
|
|
}
|
|
|
|
|
2008-02-05 07:19:16 +08:00
|
|
|
/**
|
|
|
|
* __test_and_change_bit - Change a bit and return its old value
|
|
|
|
* @nr: Bit to change
|
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is non-atomic and can be reordered.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
__test_and_change_bit (int nr, void *addr)
|
|
|
|
{
|
|
|
|
__u32 old, bit = (1 << (nr & 31));
|
|
|
|
__u32 *m = (__u32 *) addr + (nr >> 5);
|
|
|
|
|
|
|
|
old = *m;
|
|
|
|
*m = old ^ bit;
|
|
|
|
return (old & bit) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ int
|
|
|
|
test_bit (int nr, const volatile void *addr)
|
|
|
|
{
|
|
|
|
return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ffz - find the first zero bit in a long word
|
|
|
|
* @x: The long word to find the bit in
|
|
|
|
*
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
|
|
* Returns the bit-number (0..63) of the first (least significant) zero bit.
|
|
|
|
* Undefined if no zero exists, so code should check against ~0UL first...
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static inline unsigned long
|
|
|
|
ffz (unsigned long x)
|
|
|
|
{
|
|
|
|
unsigned long result;
|
|
|
|
|
|
|
|
result = ia64_popcnt(x & (~x - 1));
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* __ffs - find first bit in word.
|
|
|
|
* @x: The word to search
|
|
|
|
*
|
|
|
|
* Undefined if no bit exists, so code should check against 0 first.
|
|
|
|
*/
|
|
|
|
static __inline__ unsigned long
|
|
|
|
__ffs (unsigned long x)
|
|
|
|
{
|
|
|
|
unsigned long result;
|
|
|
|
|
|
|
|
result = ia64_popcnt((x-1) & ~x);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
|
|
/*
|
2005-04-22 02:07:59 +08:00
|
|
|
* Return bit number of last (most-significant) bit set. Undefined
|
|
|
|
* for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
static inline unsigned long
|
|
|
|
ia64_fls (unsigned long x)
|
|
|
|
{
|
|
|
|
long double d = x;
|
|
|
|
long exp;
|
|
|
|
|
|
|
|
exp = ia64_getf_exp(d);
|
|
|
|
return exp - 0xffff;
|
|
|
|
}
|
|
|
|
|
2005-04-22 02:07:59 +08:00
|
|
|
/*
|
|
|
|
* Find the last (most significant) bit set. Returns 0 for x==0 and
|
|
|
|
* bits are numbered from 1..32 (e.g., fls(9) == 4).
|
|
|
|
*/
|
2019-01-04 07:26:41 +08:00
|
|
|
static inline int fls(unsigned int t)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-04-22 02:07:59 +08:00
|
|
|
unsigned long x = t & 0xffffffffu;
|
|
|
|
|
|
|
|
if (!x)
|
|
|
|
return 0;
|
|
|
|
x |= x >> 1;
|
|
|
|
x |= x >> 2;
|
|
|
|
x |= x >> 4;
|
|
|
|
x |= x >> 8;
|
|
|
|
x |= x >> 16;
|
|
|
|
return ia64_popcnt(x);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
|
|
|
2008-03-16 01:31:49 +08:00
|
|
|
/*
|
|
|
|
* Find the last (most significant) bit set. Undefined for x==0.
|
|
|
|
* Bits are numbered from 0..63 (e.g., __fls(9) == 3).
|
|
|
|
*/
|
|
|
|
static inline unsigned long
|
|
|
|
__fls (unsigned long x)
|
|
|
|
{
|
|
|
|
x |= x >> 1;
|
|
|
|
x |= x >> 2;
|
|
|
|
x |= x >> 4;
|
|
|
|
x |= x >> 8;
|
|
|
|
x |= x >> 16;
|
|
|
|
x |= x >> 32;
|
|
|
|
return ia64_popcnt(x) - 1;
|
|
|
|
}
|
|
|
|
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
|
|
#include <asm-generic/bitops/fls64.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2013-08-14 21:06:59 +08:00
|
|
|
#include <asm-generic/bitops/builtin-ffs.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* hweightN: returns the hamming weight (i.e. the number
|
|
|
|
* of bits set) of a N-bit word
|
|
|
|
*/
|
2010-02-01 22:03:07 +08:00
|
|
|
static __inline__ unsigned long __arch_hweight64(unsigned long x)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
unsigned long result;
|
|
|
|
result = ia64_popcnt(x);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2010-02-01 22:03:07 +08:00
|
|
|
#define __arch_hweight32(x) ((unsigned int) __arch_hweight64((x) & 0xfffffffful))
|
|
|
|
#define __arch_hweight16(x) ((unsigned int) __arch_hweight64((x) & 0xfffful))
|
|
|
|
#define __arch_hweight8(x) ((unsigned int) __arch_hweight64((x) & 0xfful))
|
|
|
|
|
|
|
|
#include <asm-generic/bitops/const_hweight.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
|
|
#include <asm-generic/bitops/find.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
bitops: introduce little-endian bitops for most architectures
Introduce little-endian bit operations to the big-endian architectures
which do not have native little-endian bit operations and the
little-endian architectures. (alpha, avr32, blackfin, cris, frv, h8300,
ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa)
These architectures can just include generic implementation
(asm-generic/bitops/le.h).
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Mikael Starvik <starvik@axis.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Matthew Wilcox <willy@debian.org>
Cc: Grant Grundler <grundler@parisc-linux.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-24 07:42:02 +08:00
|
|
|
#include <asm-generic/bitops/le.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-07-27 07:09:04 +08:00
|
|
|
#include <asm-generic/bitops/ext2-atomic-setbit.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
[PATCH] bitops: ia64: use generic bitops
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
- remove sched_find_first_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-26 17:39:25 +08:00
|
|
|
#include <asm-generic/bitops/sched.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
|
|
|
|
#endif /* _ASM_IA64_BITOPS_H */
|