linux/drivers/net/ethernet/intel/ice/ice_hw_autogen.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, Intel Corporation. */

/* Machine-generated file */

#ifndef _ICE_HW_AUTOGEN_H_
#define _ICE_HW_AUTOGEN_H_

#define PF_FW_ARQBAH			0x00080180
#define PF_FW_ARQBAL			0x00080080
#define PF_FW_ARQH			0x00080380
#define PF_FW_ARQH_ARQH_S		0
#define PF_FW_ARQH_ARQH_M		ICE_M(0x3FF, PF_FW_ARQH_ARQH_S)
#define PF_FW_ARQLEN			0x00080280
#define PF_FW_ARQLEN_ARQLEN_S		0
#define PF_FW_ARQLEN_ARQLEN_M		ICE_M(0x3FF, PF_FW_ARQLEN_ARQLEN_S)
#define PF_FW_ARQLEN_ARQVFE_S		28
#define PF_FW_ARQLEN_ARQVFE_M		BIT(PF_FW_ARQLEN_ARQVFE_S)
#define PF_FW_ARQLEN_ARQOVFL_S		29
#define PF_FW_ARQLEN_ARQOVFL_M		BIT(PF_FW_ARQLEN_ARQOVFL_S)
#define PF_FW_ARQLEN_ARQCRIT_S		30
#define PF_FW_ARQLEN_ARQCRIT_M		BIT(PF_FW_ARQLEN_ARQCRIT_S)
#define PF_FW_ARQLEN_ARQENABLE_S	31
#define PF_FW_ARQLEN_ARQENABLE_M	BIT(PF_FW_ARQLEN_ARQENABLE_S)
#define PF_FW_ARQT			0x00080480
#define PF_FW_ATQBAH			0x00080100
#define PF_FW_ATQBAL			0x00080000
#define PF_FW_ATQH			0x00080300
#define PF_FW_ATQH_ATQH_S		0
#define PF_FW_ATQH_ATQH_M		ICE_M(0x3FF, PF_FW_ATQH_ATQH_S)
#define PF_FW_ATQLEN			0x00080200
#define PF_FW_ATQLEN_ATQLEN_S		0
#define PF_FW_ATQLEN_ATQLEN_M		ICE_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
#define PF_FW_ATQLEN_ATQVFE_S		28
#define PF_FW_ATQLEN_ATQVFE_M		BIT(PF_FW_ATQLEN_ATQVFE_S)
#define PF_FW_ATQLEN_ATQOVFL_S		29
#define PF_FW_ATQLEN_ATQOVFL_M		BIT(PF_FW_ATQLEN_ATQOVFL_S)
#define PF_FW_ATQLEN_ATQCRIT_S		30
#define PF_FW_ATQLEN_ATQCRIT_M		BIT(PF_FW_ATQLEN_ATQCRIT_S)
#define PF_FW_ATQLEN_ATQENABLE_S	31
#define PF_FW_ATQLEN_ATQENABLE_M	BIT(PF_FW_ATQLEN_ATQENABLE_S)
#define PF_FW_ATQT			0x00080400
#define GLGEN_RSTAT			0x000B8188
#define GLGEN_RSTAT_DEVSTATE_S		0
#define GLGEN_RSTAT_DEVSTATE_M		ICE_M(0x3, GLGEN_RSTAT_DEVSTATE_S)
#define GLGEN_RSTCTL			0x000B8180
#define GLGEN_RSTCTL_GRSTDEL_S		0
#define GLGEN_RSTCTL_GRSTDEL_M		ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
#define GLGEN_RTRIG			0x000B8190
#define GLGEN_RTRIG_CORER_S		0
#define GLGEN_RTRIG_CORER_M		BIT(GLGEN_RTRIG_CORER_S)
#define GLGEN_RTRIG_GLOBR_S		1
#define GLGEN_RTRIG_GLOBR_M		BIT(GLGEN_RTRIG_GLOBR_S)
#define GLGEN_STAT			0x000B612C
#define PFGEN_CTRL			0x00091000
#define PFGEN_CTRL_PFSWR_S		0
#define PFGEN_CTRL_PFSWR_M		BIT(PFGEN_CTRL_PFSWR_S)
#define PFHMC_ERRORDATA			0x00520500
#define PFHMC_ERRORINFO			0x00520400
#define GLINT_DYN_CTL(_INT)		(0x00160000 + ((_INT) * 4))
#define GLINT_DYN_CTL_INTENA_S		0
#define GLINT_DYN_CTL_INTENA_M		BIT(GLINT_DYN_CTL_INTENA_S)
#define GLINT_DYN_CTL_CLEARPBA_S	1
#define GLINT_DYN_CTL_CLEARPBA_M	BIT(GLINT_DYN_CTL_CLEARPBA_S)
#define GLINT_DYN_CTL_ITR_INDX_S	3
#define GLINT_DYN_CTL_SW_ITR_INDX_S	25
#define GLINT_DYN_CTL_SW_ITR_INDX_M	ICE_M(0x3, GLINT_DYN_CTL_SW_ITR_INDX_S)
#define GLINT_DYN_CTL_INTENA_MSK_S	31
#define GLINT_DYN_CTL_INTENA_MSK_M	BIT(GLINT_DYN_CTL_INTENA_MSK_S)
#define GLINT_ITR(_i, _INT)		(0x00154000 + ((_i) * 8192 + (_INT) * 4))
#define PFINT_FW_CTL			0x0016C800
#define PFINT_FW_CTL_MSIX_INDX_S	0
#define PFINT_FW_CTL_MSIX_INDX_M	ICE_M(0x7FF, PFINT_FW_CTL_MSIX_INDX_S)
#define PFINT_FW_CTL_ITR_INDX_S		11
#define PFINT_FW_CTL_ITR_INDX_M		ICE_M(0x3, PFINT_FW_CTL_ITR_INDX_S)
#define PFINT_FW_CTL_CAUSE_ENA_S	30
#define PFINT_FW_CTL_CAUSE_ENA_M	BIT(PFINT_FW_CTL_CAUSE_ENA_S)
#define PFINT_OICR			0x0016CA00
#define PFINT_OICR_INTEVENT_S		0
#define PFINT_OICR_INTEVENT_M		BIT(PFINT_OICR_INTEVENT_S)
#define PFINT_OICR_HLP_RDY_S		14
#define PFINT_OICR_HLP_RDY_M		BIT(PFINT_OICR_HLP_RDY_S)
#define PFINT_OICR_CPM_RDY_S		15
#define PFINT_OICR_CPM_RDY_M		BIT(PFINT_OICR_CPM_RDY_S)
#define PFINT_OICR_ECC_ERR_S		16
#define PFINT_OICR_ECC_ERR_M		BIT(PFINT_OICR_ECC_ERR_S)
#define PFINT_OICR_MAL_DETECT_S		19
#define PFINT_OICR_MAL_DETECT_M		BIT(PFINT_OICR_MAL_DETECT_S)
#define PFINT_OICR_GRST_S		20
#define PFINT_OICR_GRST_M		BIT(PFINT_OICR_GRST_S)
#define PFINT_OICR_PCI_EXCEPTION_S	21
#define PFINT_OICR_PCI_EXCEPTION_M	BIT(PFINT_OICR_PCI_EXCEPTION_S)
#define PFINT_OICR_GPIO_S		22
#define PFINT_OICR_GPIO_M		BIT(PFINT_OICR_GPIO_S)
#define PFINT_OICR_STORM_DETECT_S	24
#define PFINT_OICR_STORM_DETECT_M	BIT(PFINT_OICR_STORM_DETECT_S)
#define PFINT_OICR_HMC_ERR_S		26
#define PFINT_OICR_HMC_ERR_M		BIT(PFINT_OICR_HMC_ERR_S)
#define PFINT_OICR_PE_CRITERR_S		28
#define PFINT_OICR_PE_CRITERR_M		BIT(PFINT_OICR_PE_CRITERR_S)
#define PFINT_OICR_CTL			0x0016CA80
#define PFINT_OICR_CTL_MSIX_INDX_S	0
#define PFINT_OICR_CTL_MSIX_INDX_M	ICE_M(0x7FF, PFINT_OICR_CTL_MSIX_INDX_S)
#define PFINT_OICR_CTL_ITR_INDX_S	11
#define PFINT_OICR_CTL_ITR_INDX_M	ICE_M(0x3, PFINT_OICR_CTL_ITR_INDX_S)
#define PFINT_OICR_CTL_CAUSE_ENA_S	30
#define PFINT_OICR_CTL_CAUSE_ENA_M	BIT(PFINT_OICR_CTL_CAUSE_ENA_S)
#define PFINT_OICR_ENA			0x0016C900
#define GLLAN_RCTL_0			0x002941F8
#define GLNVM_FLA			0x000B6108
#define GLNVM_FLA_LOCKED_S		6
#define GLNVM_FLA_LOCKED_M		BIT(GLNVM_FLA_LOCKED_S)
#define GLNVM_GENS			0x000B6100
#define GLNVM_GENS_SR_SIZE_S		5
#define GLNVM_GENS_SR_SIZE_M		ICE_M(0x7, GLNVM_GENS_SR_SIZE_S)
#define GLNVM_ULD			0x000B6008
#define GLNVM_ULD_CORER_DONE_S		3
#define GLNVM_ULD_CORER_DONE_M		BIT(GLNVM_ULD_CORER_DONE_S)
#define GLNVM_ULD_GLOBR_DONE_S		4
#define GLNVM_ULD_GLOBR_DONE_M		BIT(GLNVM_ULD_GLOBR_DONE_S)
#define PF_FUNC_RID			0x0009E880
#define PF_FUNC_RID_FUNC_NUM_S		0
#define PF_FUNC_RID_FUNC_NUM_M		ICE_M(0x7, PF_FUNC_RID_FUNC_NUM_S)

#endif /* _ICE_HW_AUTOGEN_H_ */