2019-05-19 21:51:43 +08:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
2012-07-19 06:07:18 +08:00
|
|
|
/*
|
2013-04-11 23:55:26 +08:00
|
|
|
* Copyright 2011-2012 Calxeda, Inc.
|
|
|
|
* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
|
2012-07-19 06:07:18 +08:00
|
|
|
*
|
2013-04-11 23:55:26 +08:00
|
|
|
* Based from clk-highbank.c
|
2012-07-19 06:07:18 +08:00
|
|
|
*/
|
2013-04-11 23:55:26 +08:00
|
|
|
#include <linux/of.h>
|
2012-07-19 06:07:18 +08:00
|
|
|
|
2014-01-07 00:27:37 +08:00
|
|
|
#include "clk.h"
|
2012-07-19 06:07:18 +08:00
|
|
|
|
2014-04-14 20:59:32 +08:00
|
|
|
CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
|
|
|
|
CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
|
|
|
|
CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);
|
2015-05-20 11:22:42 +08:00
|
|
|
CLK_OF_DECLARE(socfpga_a10_pll_clk, "altr,socfpga-a10-pll-clock",
|
|
|
|
socfpga_a10_pll_init);
|
|
|
|
CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk",
|
|
|
|
socfpga_a10_periph_init);
|
|
|
|
CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk",
|
|
|
|
socfpga_a10_gate_init);
|