2008-10-23 06:47:49 +08:00
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/*
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* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/if_vlan.h>
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#include <linux/mlx4/device.h>
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#include <linux/mlx4/cmd.h>
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#include "en_port.h"
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#include "mlx4_en.h"
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2011-07-20 12:54:22 +08:00
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int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
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2008-10-23 06:47:49 +08:00
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_set_vlan_fltr_mbox *filter;
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int i;
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int j;
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int index = 0;
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u32 entry;
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int err = 0;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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filter = mailbox->buf;
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2011-07-20 12:54:22 +08:00
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for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
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entry = 0;
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for (j = 0; j < 32; j++)
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if (test_bit(index++, priv->active_vlans))
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entry |= 1 << j;
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filter->entry[i] = cpu_to_be32(entry);
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2008-10-23 06:47:49 +08:00
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}
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2011-07-20 12:54:22 +08:00
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err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
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2011-12-13 12:10:51 +08:00
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
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2008-10-23 06:47:49 +08:00
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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2010-08-24 11:46:18 +08:00
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int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
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{
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struct mlx4_en_query_port_context *qport_context;
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struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
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struct mlx4_en_port_state *state = &priv->port_state;
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struct mlx4_cmd_mailbox *mailbox;
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int err;
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mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
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2011-12-13 12:10:51 +08:00
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MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
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MLX4_CMD_WRAPPED);
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2010-08-24 11:46:18 +08:00
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if (err)
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goto out;
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qport_context = mailbox->buf;
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/* This command is always accessed from Ethtool context
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* already synchronized, no need in locking */
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state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
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2011-10-09 13:29:42 +08:00
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switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
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2014-10-27 17:37:39 +08:00
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case MLX4_EN_100M_SPEED:
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state->link_speed = SPEED_100;
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break;
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2011-10-09 13:29:42 +08:00
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case MLX4_EN_1G_SPEED:
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2014-10-27 17:37:39 +08:00
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state->link_speed = SPEED_1000;
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2011-10-09 13:29:42 +08:00
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break;
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case MLX4_EN_10G_SPEED_XAUI:
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case MLX4_EN_10G_SPEED_XFI:
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2014-10-27 17:37:39 +08:00
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state->link_speed = SPEED_10000;
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break;
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case MLX4_EN_20G_SPEED:
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state->link_speed = SPEED_20000;
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2011-10-09 13:29:42 +08:00
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break;
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case MLX4_EN_40G_SPEED:
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2014-10-27 17:37:39 +08:00
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state->link_speed = SPEED_40000;
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break;
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case MLX4_EN_56G_SPEED:
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state->link_speed = SPEED_56000;
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2011-10-09 13:29:42 +08:00
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break;
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default:
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state->link_speed = -1;
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break;
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}
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2014-10-27 17:37:40 +08:00
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state->transceiver = qport_context->transceiver;
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state->flags = 0; /* Reset and recalculate the port flags */
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state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
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MLX4_EN_PORT_ANC : 0;
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state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
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MLX4_EN_PORT_ANE : 0;
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2010-08-24 11:46:18 +08:00
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out:
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mlx4_free_cmd_mailbox(mdev->dev, mailbox);
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return err;
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}
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2008-10-23 06:47:49 +08:00
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2015-03-30 22:45:26 +08:00
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/* Each counter set is located in struct mlx4_en_stat_out_mbox
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* with a const offset between its prio components.
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* This function runs over a counter set and sum all of it's prio components.
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*/
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static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num)
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{
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__be64 *curr = start;
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unsigned long ret = 0;
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int i;
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int offset = next - start;
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2015-05-05 22:07:11 +08:00
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for (i = 0; i < num; i++) {
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2015-03-30 22:45:26 +08:00
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ret += be64_to_cpu(*curr);
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curr += offset;
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}
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return ret;
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}
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2008-10-23 06:47:49 +08:00
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int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
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{
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2015-06-15 22:59:06 +08:00
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struct mlx4_counter tmp_counter_stats;
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2008-10-23 06:47:49 +08:00
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struct mlx4_en_stat_out_mbox *mlx4_en_stats;
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2015-03-30 22:45:25 +08:00
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struct mlx4_en_stat_out_flow_control_mbox *flowstats;
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2008-10-23 06:47:49 +08:00
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struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
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struct net_device_stats *stats = &priv->stats;
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struct mlx4_cmd_mailbox *mailbox;
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u64 in_mod = reset << 8 | port;
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int err;
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2015-06-15 22:59:06 +08:00
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int i, counter_index;
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2016-04-20 21:01:18 +08:00
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unsigned long sw_rx_dropped = 0;
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2008-10-23 06:47:49 +08:00
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mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
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2011-12-13 12:10:51 +08:00
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MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
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MLX4_CMD_WRAPPED);
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2008-10-23 06:47:49 +08:00
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if (err)
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goto out;
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mlx4_en_stats = mailbox->buf;
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spin_lock_bh(&priv->stats_lock);
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2009-04-20 12:34:38 +08:00
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stats->rx_packets = 0;
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stats->rx_bytes = 0;
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2011-10-18 09:50:56 +08:00
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priv->port_stats.rx_chksum_good = 0;
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priv->port_stats.rx_chksum_none = 0;
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2014-11-09 19:51:53 +08:00
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priv->port_stats.rx_chksum_complete = 0;
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2009-04-20 12:34:38 +08:00
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for (i = 0; i < priv->rx_ring_num; i++) {
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2013-11-07 18:19:52 +08:00
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stats->rx_packets += priv->rx_ring[i]->packets;
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stats->rx_bytes += priv->rx_ring[i]->bytes;
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2016-04-20 21:01:18 +08:00
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sw_rx_dropped += priv->rx_ring[i]->dropped;
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2013-11-07 18:19:52 +08:00
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priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok;
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priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none;
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2014-11-09 19:51:53 +08:00
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priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete;
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2009-04-20 12:34:38 +08:00
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}
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stats->tx_packets = 0;
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stats->tx_bytes = 0;
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2016-05-26 00:50:36 +08:00
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stats->tx_dropped = 0;
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2011-10-18 09:50:56 +08:00
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priv->port_stats.tx_chksum_offload = 0;
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2014-03-02 16:25:00 +08:00
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priv->port_stats.queue_stopped = 0;
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priv->port_stats.wake_queue = 0;
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2014-10-02 23:24:21 +08:00
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priv->port_stats.tso_packets = 0;
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priv->port_stats.xmit_more = 0;
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2014-03-02 16:25:00 +08:00
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2011-03-23 06:37:23 +08:00
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for (i = 0; i < priv->tx_ring_num; i++) {
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2014-10-02 23:24:21 +08:00
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const struct mlx4_en_tx_ring *ring = priv->tx_ring[i];
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stats->tx_packets += ring->packets;
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stats->tx_bytes += ring->bytes;
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2016-05-26 00:50:36 +08:00
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stats->tx_dropped += ring->tx_dropped;
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2014-10-02 23:24:21 +08:00
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priv->port_stats.tx_chksum_offload += ring->tx_csum;
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priv->port_stats.queue_stopped += ring->queue_stopped;
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priv->port_stats.wake_queue += ring->wake_queue;
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priv->port_stats.tso_packets += ring->tso_packets;
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priv->port_stats.xmit_more += ring->xmit_more;
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2009-04-20 12:34:38 +08:00
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}
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2015-06-23 22:14:13 +08:00
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if (mlx4_is_master(mdev->dev)) {
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stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0,
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&mlx4_en_stats->RTOT_prio_1,
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NUM_PRIORITIES);
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stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0,
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&mlx4_en_stats->TTOT_prio_1,
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NUM_PRIORITIES);
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stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0,
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&mlx4_en_stats->ROCT_prio_1,
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NUM_PRIORITIES);
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stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0,
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&mlx4_en_stats->TOCT_prio_1,
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NUM_PRIORITIES);
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}
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2008-10-23 06:47:49 +08:00
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2015-03-30 22:45:26 +08:00
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/* net device stats */
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2008-10-23 06:47:49 +08:00
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stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
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be32_to_cpu(mlx4_en_stats->RJBBR) +
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be32_to_cpu(mlx4_en_stats->RCRC) +
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2015-03-30 22:45:26 +08:00
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be32_to_cpu(mlx4_en_stats->RRUNT) +
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be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
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be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
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be32_to_cpu(mlx4_en_stats->RSHORT) +
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en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
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&mlx4_en_stats->RGIANT_prio_1,
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NUM_PRIORITIES);
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stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
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&mlx4_en_stats->TGIANT_prio_1,
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NUM_PRIORITIES);
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stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
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&mlx4_en_stats->MCAST_prio_1,
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NUM_PRIORITIES);
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2008-10-23 06:47:49 +08:00
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stats->collisions = 0;
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2016-04-20 21:01:18 +08:00
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stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP) +
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sw_rx_dropped;
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2008-10-23 06:47:49 +08:00
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stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
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2016-02-17 23:24:22 +08:00
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stats->rx_over_errors = 0;
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2008-10-23 06:47:49 +08:00
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stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
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stats->rx_frame_errors = 0;
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stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
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2016-02-17 23:24:22 +08:00
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stats->rx_missed_errors = 0;
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2008-10-23 06:47:49 +08:00
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stats->tx_aborted_errors = 0;
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stats->tx_carrier_errors = 0;
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stats->tx_fifo_errors = 0;
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stats->tx_heartbeat_errors = 0;
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stats->tx_window_errors = 0;
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2016-05-26 00:50:36 +08:00
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stats->tx_dropped += be32_to_cpu(mlx4_en_stats->TDROP);
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2015-03-30 22:45:26 +08:00
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/* RX stats */
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priv->pkstats.rx_multicast_packets = stats->multicast;
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priv->pkstats.rx_broadcast_packets =
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en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
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&mlx4_en_stats->RBCAST_prio_1,
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NUM_PRIORITIES);
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priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
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priv->pkstats.rx_in_range_length_error =
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be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
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priv->pkstats.rx_out_range_length_error =
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be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);
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/* Tx stats */
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priv->pkstats.tx_multicast_packets =
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en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
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&mlx4_en_stats->TMCAST_prio_1,
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NUM_PRIORITIES);
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priv->pkstats.tx_broadcast_packets =
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en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
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&mlx4_en_stats->TBCAST_prio_1,
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NUM_PRIORITIES);
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|
|
|
|
|
priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
|
|
|
|
priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
|
|
|
|
priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
|
|
|
|
priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
|
|
|
|
priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
|
|
|
|
priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
|
|
|
|
priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
|
|
|
|
priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
|
|
|
|
priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
|
|
|
|
priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
|
|
|
|
priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
|
|
|
|
priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
|
|
|
|
priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
|
|
|
|
priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
|
|
|
|
priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
|
|
|
|
priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
|
|
|
|
priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
|
|
|
|
priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
|
|
|
|
priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
|
|
|
|
priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
|
|
|
|
priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
|
|
|
|
priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
|
|
|
|
priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
|
|
|
|
priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
|
|
|
|
priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
|
|
|
|
priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
|
|
|
|
priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
|
|
|
|
priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
|
|
|
|
priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
|
|
|
|
priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
|
|
|
|
priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
|
|
|
|
priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
|
|
|
|
priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
|
|
|
|
priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
|
|
|
|
priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
|
|
|
|
priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);
|
2008-10-23 06:47:49 +08:00
|
|
|
|
|
|
|
spin_unlock_bh(&priv->stats_lock);
|
|
|
|
|
2015-06-15 22:59:06 +08:00
|
|
|
memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats));
|
|
|
|
counter_index = mlx4_get_default_counter_index(mdev->dev, port);
|
|
|
|
err = mlx4_get_counter_stats(mdev->dev, counter_index,
|
|
|
|
&tmp_counter_stats, reset);
|
|
|
|
|
2015-03-30 22:45:25 +08:00
|
|
|
/* 0xffs indicates invalid value */
|
|
|
|
memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
|
|
|
|
|
|
|
|
if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
|
|
|
|
memset(mailbox->buf, 0,
|
|
|
|
sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
|
|
|
|
err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
|
|
|
|
in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
|
|
|
|
0, MLX4_CMD_DUMP_ETH_STATS,
|
|
|
|
MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
flowstats = mailbox->buf;
|
|
|
|
|
|
|
|
spin_lock_bh(&priv->stats_lock);
|
|
|
|
|
2015-06-15 22:59:06 +08:00
|
|
|
if (tmp_counter_stats.counter_mode == 0) {
|
|
|
|
priv->pf_stats.rx_bytes = be64_to_cpu(tmp_counter_stats.rx_bytes);
|
|
|
|
priv->pf_stats.tx_bytes = be64_to_cpu(tmp_counter_stats.tx_bytes);
|
|
|
|
priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames);
|
|
|
|
priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames);
|
|
|
|
}
|
|
|
|
|
2015-03-30 22:45:25 +08:00
|
|
|
for (i = 0; i < MLX4_NUM_PRIORITIES; i++) {
|
|
|
|
priv->rx_priority_flowstats[i].rx_pause =
|
|
|
|
be64_to_cpu(flowstats[i].rx_pause);
|
|
|
|
priv->rx_priority_flowstats[i].rx_pause_duration =
|
|
|
|
be64_to_cpu(flowstats[i].rx_pause_duration);
|
|
|
|
priv->rx_priority_flowstats[i].rx_pause_transition =
|
|
|
|
be64_to_cpu(flowstats[i].rx_pause_transition);
|
|
|
|
priv->tx_priority_flowstats[i].tx_pause =
|
|
|
|
be64_to_cpu(flowstats[i].tx_pause);
|
|
|
|
priv->tx_priority_flowstats[i].tx_pause_duration =
|
|
|
|
be64_to_cpu(flowstats[i].tx_pause_duration);
|
|
|
|
priv->tx_priority_flowstats[i].tx_pause_transition =
|
|
|
|
be64_to_cpu(flowstats[i].tx_pause_transition);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if pfc is not in use, all priorities counters have the same value */
|
|
|
|
priv->rx_flowstats.rx_pause =
|
|
|
|
be64_to_cpu(flowstats[0].rx_pause);
|
|
|
|
priv->rx_flowstats.rx_pause_duration =
|
|
|
|
be64_to_cpu(flowstats[0].rx_pause_duration);
|
|
|
|
priv->rx_flowstats.rx_pause_transition =
|
|
|
|
be64_to_cpu(flowstats[0].rx_pause_transition);
|
|
|
|
priv->tx_flowstats.tx_pause =
|
|
|
|
be64_to_cpu(flowstats[0].tx_pause);
|
|
|
|
priv->tx_flowstats.tx_pause_duration =
|
|
|
|
be64_to_cpu(flowstats[0].tx_pause_duration);
|
|
|
|
priv->tx_flowstats.tx_pause_transition =
|
|
|
|
be64_to_cpu(flowstats[0].tx_pause_transition);
|
|
|
|
|
|
|
|
spin_unlock_bh(&priv->stats_lock);
|
|
|
|
|
2008-10-23 06:47:49 +08:00
|
|
|
out:
|
|
|
|
mlx4_free_cmd_mailbox(mdev->dev, mailbox);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|