openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity
linux/arch/m68k/include/asm/m528xsim.h

257 lines
9.4 KiB
C
Raw Normal View History

License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
/* SPDX-License-Identifier: GPL-2.0 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/****************************************************************************/
/*
* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m528xsim_h
#define m528xsim_h
/****************************************************************************/
m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:40:37 +08:00
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
m68knommu: remove ColdFire CLOCK_DIV config option The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 12:19:08 +08:00
#define MCF_BUSCLK MCF_CLK
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-09 08:12:29 +08:00
#include <asm/m52xxacr.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/*
* Define the 5280/5282 SIM register set addresses.
*/
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 20:17:17 +08:00
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
m68knommu: make 528x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:39:04 +08:00
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
#define MCFINT_I2C0 17 /* Interrupt number for I2C */
m68knommu: Coldfire QSPI platform support Since Grant has added the coldfire-qspi driver to next-spi, here is the platform support for the parts that have qspi hardware. This sets up gpio to do the spi chip select using the default chip select pins; it should be trivial for boards that require different or additional spi chip selects to use other gpios as needed. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-01-23 04:43:03 +08:00
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
m68knommu: make 528x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:20:02 +08:00
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
m68knommu: make 528x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:39:04 +08:00
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
m68knommu: make 528x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:20:02 +08:00
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
m68knommu: make 528x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:42:30 +08:00
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 so we can support those parts that have the pit1 interrupt on other than the first interrupt controller. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-06-07 05:02:14 +08:00
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/*
* SDRAM configuration registers.
*/
m68knommu: clean up use of MBAR for DRAM registers on ColdFire start In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-06 21:01:46 +08:00
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
m68knommu: move ColdFire DMA register addresses to per-cpu headers The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 22:54:36 +08:00
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
/*
* UART module.
*/
m68knommu: make 528x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:39:04 +08:00
#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
m68knommu: remove use of MBAR value for ColdFire 528x peripheral addressing The ColdFire 528x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 22:20:01 +08:00
/*
* FEC ethernet module.
*/
m68knommu: make 528x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:20:02 +08:00
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
#define MCFFEC_SIZE0 0x800
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
m68knommu: make 528x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:42:30 +08:00
/*
* QSPI module.
*/
m68knommu: m528x qspi definition fix The consolidation of the qspi code missed a definition for 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-05-06 04:40:44 +08:00
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
m68knommu: make 528x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:42:30 +08:00
#define MCFQSPI_SIZE 0x40
#define MCFQSPI_CS0 147
#define MCFQSPI_CS1 148
#define MCFQSPI_CS2 149
#define MCFQSPI_CS3 150
generic GPIO support for the Freescale Coldfire 528x. Add support for the 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:08 +08:00
/*
* GPIO registers
*/
m68knommu: switch to GPIO init macros in ColdFire 528x init code Modify the GPIO setup table to use the mcfgpio.h macros for table init. Simplifies code and reduces line count significantly. We also need to rename some of the GPIO registers to be consistent with all other ColdFire parts (we can't use the new GPIO macros otherwise). Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Steven King <sfking@fdwdc.com>
2012-04-16 14:59:37 +08:00
#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
generic GPIO support for the Freescale Coldfire 528x. Add support for the 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:08 +08:00
#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
m68knommu: move ColdFire PIT timer base addresses The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 21:32:35 +08:00
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
generic GPIO support for the Freescale Coldfire 528x. Add support for the 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:08 +08:00
/*
* Edge Port registers
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
/*
* Queued ADC registers
*/
#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
/*
* General Purpose Timers registers
*/
#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
/*
*
* definitions for generic gpio support
*
*/
m68knommu: switch to GPIO init macros in ColdFire 528x init code Modify the GPIO setup table to use the mcfgpio.h macros for table init. Simplifies code and reduces line count significantly. We also need to rename some of the GPIO registers to be consistent with all other ColdFire parts (we can't use the new GPIO macros otherwise). Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Steven King <sfking@fdwdc.com>
2012-04-16 14:59:37 +08:00
#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
generic GPIO support for the Freescale Coldfire 528x. Add support for the 528x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:08 +08:00
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCFGPIO_PIN_MAX 180
m68knommu: move CPU reset code for the 528x ColdFire into its platform code Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-04-30 21:15:56 +08:00
/*
* Reset Control Unit (relative to IPSBAR).
*/
m68knommu: make 528x CPU reset register addressing consistent If we make all MCF_RCR (CPU reset register) addressing consistent across all ColdFire CPU family members that use it then we will be able to remove the duplicated copies of the code that use it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-02-19 14:34:58 +08:00
#define MCF_RCR (MCF_IPSBAR + 0x110000)
#define MCF_RSR (MCF_IPSBAR + 0x110001)
m68knommu: move CPU reset code for the 528x ColdFire into its platform code Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-04-30 21:15:56 +08:00
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
[PATCH] m68knommu: add SPI register definitions for 528x processors Add QSPI register definitions of ColdFIre 528x processor SPI controller. Patch originally submitted by Derek Cheung <derek.cheung@sympatico.ca> Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-12 09:18:10 +08:00
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
/*
* I2C module
*/
#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
#define MCFI2C_SIZE0 0x40
m68knommu: remove unused ColdFire 5282 register definitions There is a bunch of old unused and ugly register definitions in the ColdFire 5282 header. Remove them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 21:36:52 +08:00
/****************************************************************************/
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#endif /* m528xsim_h */