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linux/arch/m68k/include/asm/m53xxsim.h

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
/* SPDX-License-Identifier: GPL-2.0 */
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/****************************************************************************/
/*
m68knommu: create and use a common M53xx ColdFire class of CPUs The current CONFIG_M532x support definitions are actually common to a larger set of version 3 ColdFire CPU types. In the future we want to add support for the 537x family. It is very similar to the 532x internally, and will be able to use most of the same definitions. Create a CONFIG_M53xx option that is enabled to support any of the common 532x and 537x CPU types. Convert the current users of CONFIG_M532x to use CONFIG_M53xx instead. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-11-05 10:01:38 +08:00
* m53xxsim.h -- ColdFire 5329 registers
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
*/
/****************************************************************************/
m68knommu: create and use a common M53xx ColdFire class of CPUs The current CONFIG_M532x support definitions are actually common to a larger set of version 3 ColdFire CPU types. In the future we want to add support for the 537x family. It is very similar to the 532x internally, and will be able to use most of the same definitions. Create a CONFIG_M53xx option that is enabled to support any of the common 532x and 537x CPU types. Convert the current users of CONFIG_M532x to use CONFIG_M53xx instead. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-11-05 10:01:38 +08:00
#ifndef m53xxsim_h
#define m53xxsim_h
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/****************************************************************************/
m68knommu: create and use a common M53xx ColdFire class of CPUs The current CONFIG_M532x support definitions are actually common to a larger set of version 3 ColdFire CPU types. In the future we want to add support for the 537x family. It is very similar to the 532x internally, and will be able to use most of the same definitions. Create a CONFIG_M53xx option that is enabled to support any of the common 532x and 537x CPU types. Convert the current users of CONFIG_M532x to use CONFIG_M53xx instead. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-11-05 10:01:38 +08:00
#define CPU_NAME "COLDFIRE(m53xx)"
m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:40:37 +08:00
#define CPU_INSTR_PER_JIFFY 3
m68knommu: remove ColdFire CLOCK_DIV config option The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 12:19:08 +08:00
#define MCF_BUSCLK (MCF_CLK / 3)
m68knommu: move ColdFire CPU names into their headers Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:13:27 +08:00
m68knommu: merge bit definitions for version 3 ColdFire cache controller All version 3 based ColdFire CPU cores have a similar cache controller. Merge all the exitsing definitions into a single file, and make them similar in style and naming to the existing version 2 and version 4 cache controller definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-09 08:19:45 +08:00
#include <asm/m53xxacr.h>
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
#define MCFINT_VECBASE 64
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
m68knommu: add missing interrupt line definition for UART 2 Signed-off-by: David Wu <david.wu@arcturusnetworks.com> Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com> Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-02-12 14:02:05 +08:00
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
#define MCFINT_I2C0 30 /* Interrupt number for I2C */
m68knommu: Coldfire QSPI platform support Since Grant has added the coldfire-qspi driver to next-spi, here is the platform support for the parts that have qspi hardware. This sets up gpio to do the spi chip select using the default chip select pins; it should be trivial for boards that require different or additional spi chip selects to use other gpios as needed. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-01-23 04:43:03 +08:00
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
m68knommu: make 532x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:23:01 +08:00
#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
m68knommu: make 532x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:41:07 +08:00
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
m68knommu: make 532x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:23:01 +08:00
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
m68knommu: make 532x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 532x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:44:45 +08:00
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_WTM_WCR 0xFC098000
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/*
* Define the 532x SIM register set addresses.
*/
#define MCFSIM_IPRL 0xFC048004
#define MCFSIM_IPRH 0xFC048000
#define MCFSIM_IPR MCFSIM_IPRL
#define MCFSIM_IMRL 0xFC04800C
#define MCFSIM_IMRH 0xFC048008
#define MCFSIM_IMR MCFSIM_IMRL
#define MCFSIM_ICR0 0xFC048040
#define MCFSIM_ICR1 0xFC048041
#define MCFSIM_ICR2 0xFC048042
#define MCFSIM_ICR3 0xFC048043
#define MCFSIM_ICR4 0xFC048044
#define MCFSIM_ICR5 0xFC048045
#define MCFSIM_ICR6 0xFC048046
#define MCFSIM_ICR7 0xFC048047
#define MCFSIM_ICR8 0xFC048048
#define MCFSIM_ICR9 0xFC048049
#define MCFSIM_ICR10 0xFC04804A
#define MCFSIM_ICR11 0xFC04804B
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
m68knommu: general interrupt controller for ColdFire 532x parts The ColdFire 532x family of parts uses 2 of the same INTC interrupt controlers used in the ColdFire 520x family. So modify the code to support both parts. The extra code for the second INTC controler in the case of the 520x is easily optimized away to nothing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-04-29 10:07:13 +08:00
#define MCFINTC0_SIMR 0xFC04801C
#define MCFINTC0_CIMR 0xFC04801D
#define MCFINTC0_ICR0 0xFC048040
#define MCFINTC1_SIMR 0xFC04C01C
#define MCFINTC1_CIMR 0xFC04C01D
#define MCFINTC1_ICR0 0xFC04C040
m68knommu: add definitions for the third interrupt controller on devices that don't have a third interrupt controller. Extending the interrupt controller code in intc-simr.c to support the third interrupt controller on the m5441x means we need to add defines (as 0) for the third interrupt controller on devices that don't have a third interrupt controller. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-06-09 05:15:29 +08:00
#define MCFINTC2_SIMR (0)
#define MCFINTC2_CIMR (0)
#define MCFINTC2_ICR0 (0)
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
m68knommu: clean up ColdFire 532x CPU timer setup The newer ColdFire 532x family of CPU's uses the old timer, but has a newer interrupt controller. It doesn't need the special timer setup that was required when using the older interrupt controller. Remove the dead timer irq and level setting code, and define the hard coded vector. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-05-19 13:00:01 +08:00
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
/*
* UART module.
*/
m68knommu: make 532x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 22:41:07 +08:00
#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
m68knommu: make 532x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 08:23:01 +08:00
/*
* FEC module.
*/
#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
m68knommu: make 532x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 532x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:44:45 +08:00
/*
* QSPI module.
*/
m68knommu: fix ColdFire 5373/5329 QSPI base address The base address of the QSPI hardware module should be 0xFC05C000. Fix its definition. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2013-01-25 12:21:11 +08:00
#define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
m68knommu: make 532x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 532x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-24 10:44:45 +08:00
#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
#define MCFQSPI_CS0 84
#define MCFQSPI_CS1 85
#define MCFQSPI_CS2 86
m68knommu: remove use of MBAR in old-style ColdFire timer Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 07:57:14 +08:00
/*
* Timer module.
*/
#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
m68knommu: add CPU reset code for the 532x ColdFire Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-04-30 20:03:43 +08:00
/*********************************************************************
*
* Reset Controller Module
*
*********************************************************************/
#define MCF_RCR 0xFC0A0000
#define MCF_RSR 0xFC0A0001
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
m68knommu: Add clk definitions for m532x. The 532x has individually controllable clocks for it peripherals. Add clk definitions for these and add default initialization of either enabled or disabled. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-06-17 15:41:39 +08:00
/*
* Power Management
*/
#define MCFPM_WCR 0xfc040013
#define MCFPM_PPMSR0 0xfc04002c
#define MCFPM_PPMCR0 0xfc04002d
#define MCFPM_PPMSR1 0xfc04002e
#define MCFPM_PPMCR1 0xfc04002f
#define MCFPM_PPMHR0 0xfc040030
#define MCFPM_PPMLR0 0xfc040034
#define MCFPM_PPMHR1 0xfc040038
#define MCFPM_LPCR 0xec090007
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/*
* The M5329EVB board needs a help getting its devices initialized
* at kernel start time if dBUG doesn't set it up (for example
* it is not used), so we need to do it manually.
*/
#ifdef __ASSEMBLER__
.macro m5329EVB_setup
movel #0xFC098000, %a7
movel #0x0, (%a7)
#define CORE_SRAM 0x80000000
#define CORE_SRAM_SIZE 0x8000
movel #CORE_SRAM, %d0
addl #0x221, %d0
movec %d0,%RAMBAR1
movel #CORE_SRAM, %sp
addl #CORE_SRAM_SIZE, %sp
jsr sysinit
.endm
#define PLATFORM_SETUP m5329EVB_setup
#endif /* __ASSEMBLER__ */
/*********************************************************************
*
* Chip Configuration Module (CCM)
*
*********************************************************************/
/* Register read/write macros */
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_CCM_CCR 0xFC0A0004
#define MCF_CCM_RCON 0xFC0A0008
#define MCF_CCM_CIR 0xFC0A000A
#define MCF_CCM_MISCCR 0xFC0A0010
#define MCF_CCM_CDR 0xFC0A0012
#define MCF_CCM_UHCSR 0xFC0A0014
#define MCF_CCM_UOCSR 0xFC0A0016
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/* Bit definitions and macros for MCF_CCM_CCR */
#define MCF_CCM_CCR_RESERVED (0x0001)
#define MCF_CCM_CCR_PLL_MODE (0x0003)
#define MCF_CCM_CCR_OSC_MODE (0x0005)
#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
#define MCF_CCM_CCR_LOAD (0x0021)
#define MCF_CCM_CCR_LIMP (0x0041)
#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
/* Bit definitions and macros for MCF_CCM_RCON */
#define MCF_CCM_RCON_RESERVED (0x0001)
#define MCF_CCM_RCON_PLL_MODE (0x0003)
#define MCF_CCM_RCON_OSC_MODE (0x0005)
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
#define MCF_CCM_RCON_LOAD (0x0021)
#define MCF_CCM_RCON_LIMP (0x0041)
#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
/* Bit definitions and macros for MCF_CCM_CIR */
#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
/* Bit definitions and macros for MCF_CCM_MISCCR */
#define MCF_CCM_MISCCR_USBSRC (0x0001)
#define MCF_CCM_MISCCR_USBDIV (0x0002)
#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
#define MCF_CCM_MISCCR_LIMP (0x1000)
#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
/* Bit definitions and macros for MCF_CCM_CDR */
#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
/* Bit definitions and macros for MCF_CCM_UHCSR */
#define MCF_CCM_UHCSR_XPDE (0x0001)
#define MCF_CCM_UHCSR_UHMIE (0x0002)
#define MCF_CCM_UHCSR_WKUP (0x0004)
#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
/* Bit definitions and macros for MCF_CCM_UOCSR */
#define MCF_CCM_UOCSR_XPDE (0x0001)
#define MCF_CCM_UOCSR_UOMIE (0x0002)
#define MCF_CCM_UOCSR_WKUP (0x0004)
#define MCF_CCM_UOCSR_PWRFLT (0x0008)
#define MCF_CCM_UOCSR_SEND (0x0010)
#define MCF_CCM_UOCSR_VVLD (0x0020)
#define MCF_CCM_UOCSR_BVLD (0x0040)
#define MCF_CCM_UOCSR_AVLD (0x0080)
#define MCF_CCM_UOCSR_DPPU (0x0100)
#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
#define MCF_CCM_UOCSR_DMPD (0x1000)
#define MCF_CCM_UOCSR_DPPD (0x2000)
#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
/*********************************************************************
*
* FlexBus Chip Selects (FBCS)
*
*********************************************************************/
/* Register read/write macros */
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_FBCS0_CSAR 0xFC008000
#define MCF_FBCS0_CSMR 0xFC008004
#define MCF_FBCS0_CSCR 0xFC008008
#define MCF_FBCS1_CSAR 0xFC00800C
#define MCF_FBCS1_CSMR 0xFC008010
#define MCF_FBCS1_CSCR 0xFC008014
#define MCF_FBCS2_CSAR 0xFC008018
#define MCF_FBCS2_CSMR 0xFC00801C
#define MCF_FBCS2_CSCR 0xFC008020
#define MCF_FBCS3_CSAR 0xFC008024
#define MCF_FBCS3_CSMR 0xFC008028
#define MCF_FBCS3_CSCR 0xFC00802C
#define MCF_FBCS4_CSAR 0xFC008030
#define MCF_FBCS4_CSMR 0xFC008034
#define MCF_FBCS4_CSCR 0xFC008038
#define MCF_FBCS5_CSAR 0xFC00803C
#define MCF_FBCS5_CSMR 0xFC008040
#define MCF_FBCS5_CSCR 0xFC008044
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_FBCS_CSMR */
#define MCF_FBCS_CSMR_V (0x00000001)
#define MCF_FBCS_CSMR_WP (0x00000100)
#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for MCF_FBCS_CSCR */
#define MCF_FBCS_CSCR_BSTW (0x00000008)
#define MCF_FBCS_CSCR_BSTR (0x00000010)
#define MCF_FBCS_CSCR_BEM (0x00000020)
#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
#define MCF_FBCS_CSCR_AA (0x00000100)
#define MCF_FBCS_CSCR_SBM (0x00000200)
#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
#define MCF_FBCS_CSCR_SWSEN (0x00800000)
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
#define MCF_FBCS_CSCR_PS_8 (0x0040)
#define MCF_FBCS_CSCR_PS_16 (0x0080)
#define MCF_FBCS_CSCR_PS_32 (0x0000)
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
generic GPIO support for the Freescale Coldfire 532x. Add support for the 532x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:10 +08:00
#define MCFGPIO_PODR_FECH (0xFC0A4000)
#define MCFGPIO_PODR_FECL (0xFC0A4001)
#define MCFGPIO_PODR_SSI (0xFC0A4002)
#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
#define MCFGPIO_PODR_BE (0xFC0A4004)
#define MCFGPIO_PODR_CS (0xFC0A4005)
#define MCFGPIO_PODR_PWM (0xFC0A4006)
#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
#define MCFGPIO_PODR_UART (0xFC0A4009)
#define MCFGPIO_PODR_QSPI (0xFC0A400A)
#define MCFGPIO_PODR_TIMER (0xFC0A400B)
#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
#define MCFGPIO_PDDR_FECH (0xFC0A4014)
#define MCFGPIO_PDDR_FECL (0xFC0A4015)
#define MCFGPIO_PDDR_SSI (0xFC0A4016)
#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
#define MCFGPIO_PDDR_BE (0xFC0A4018)
#define MCFGPIO_PDDR_CS (0xFC0A4019)
#define MCFGPIO_PDDR_PWM (0xFC0A401A)
#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
#define MCFGPIO_PDDR_UART (0xFC0A401C)
#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
#define MCFGPIO_PCLRR_BE (0xFC0A4040)
#define MCFGPIO_PCLRR_CS (0xFC0A4041)
#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
#define MCFGPIO_PCLRR_UART (0xFC0A4045)
#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
m68knommu: modify ColdFire 532x GPIO register definitions to be consistent The ColdFire 532x CPU register definitions for the multi-function setup pins are inconsistently defined compared with other ColdFire parts. Modify the register defintions to be just the addresses, not pointers. This also fixes the erroneous use in one case of using these values in the UART setup code for the 532x. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 13:26:25 +08:00
#define MCFGPIO_PAR_FEC (0xFC0A4050)
#define MCFGPIO_PAR_PWM (0xFC0A4051)
#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
#define MCFGPIO_PAR_BE (0xFC0A4054)
#define MCFGPIO_PAR_CS (0xFC0A4055)
#define MCFGPIO_PAR_SSI (0xFC0A4056)
#define MCFGPIO_PAR_UART (0xFC0A4058)
#define MCFGPIO_PAR_QSPI (0xFC0A405A)
#define MCFGPIO_PAR_TIMER (0xFC0A405C)
#define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
#define MCFGPIO_PAR_IRQ (0xFC0A4060)
#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
#define MCFGPIO_DSCR_I2C (0xFC0A4068)
#define MCFGPIO_DSCR_PWM (0xFC0A4069)
#define MCFGPIO_DSCR_FEC (0xFC0A406A)
#define MCFGPIO_DSCR_UART (0xFC0A406B)
#define MCFGPIO_DSCR_QSPI (0xFC0A406C)
#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
#define MCFGPIO_DSCR_SSI (0xFC0A406E)
#define MCFGPIO_DSCR_LCD (0xFC0A406F)
#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
#define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
#define MCFGPIO_DSCR_IRQ (0xFC0A4072)
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_BE */
#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_CS */
#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_UART */
#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
/* Bit definitions and macros for MCF_GPIO_PAR_BE */
#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
/* Bit definitions and macros for MCF_GPIO_PAR_CS */
#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
/* Bit definitions and macros for MCF_GPIO_PAR_UART */
#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
generic GPIO support for the Freescale Coldfire 532x. Add support for the 532x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:10 +08:00
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_FECH
#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
#define MCFGPIO_PIN_MAX 136
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/*********************************************************************
*
* Phase Locked Loop (PLL)
*
*********************************************************************/
/* Register read/write macros */
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_PLL_PODR 0xFC0C0000
#define MCF_PLL_PLLCR 0xFC0C0004
#define MCF_PLL_PMDR 0xFC0C0008
#define MCF_PLL_PFDR 0xFC0C000C
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/* Bit definitions and macros for MCF_PLL_PODR */
#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
/* Bit definitions and macros for MCF_PLL_PLLCR */
#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
#define MCF_PLL_PLLCR_DITHEN (0x80)
/* Bit definitions and macros for MCF_PLL_PMDR */
#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PLL_PFDR */
#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
/*********************************************************************
*
* System Control Module Registers (SCM)
*
*********************************************************************/
/* Register read/write macros */
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_SCM_MPR 0xFC000000
#define MCF_SCM_PACRA 0xFC000020
#define MCF_SCM_PACRB 0xFC000024
#define MCF_SCM_PACRC 0xFC000028
#define MCF_SCM_PACRD 0xFC00002C
#define MCF_SCM_PACRE 0xFC000040
#define MCF_SCM_PACRF 0xFC000044
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_SCM_BCR 0xFC040024
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/*********************************************************************
*
* SDRAM Controller (SDRAMC)
*
*********************************************************************/
/* Register read/write macros */
m68knommu: use read/write IO access functions in ColdFire m532x setup code Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 14:16:19 +08:00
#define MCF_SDRAMC_SDMR 0xFC0B8000
#define MCF_SDRAMC_SDCR 0xFC0B8004
#define MCF_SDRAMC_SDCFG1 0xFC0B8008
#define MCF_SDRAMC_SDCFG2 0xFC0B800C
#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
#define MCF_SDRAMC_SDDS 0xFC0B8100
#define MCF_SDRAMC_SDCS0 0xFC0B8110
#define MCF_SDRAMC_SDCS1 0xFC0B8114
#define MCF_SDRAMC_SDCS2 0xFC0B8118
#define MCF_SDRAMC_SDCS3 0xFC0B811C
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x00010000)
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
#define MCF_SDRAMC_SDCR_IREF (0x00000004)
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
#define MCF_SDRAMC_SDCR_REF (0x10000000)
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
/* Device Errata - LIMP mode work around */
#define MCF_SDRAMC_REFRESH (0x40000000)
/* Bit definitions and macros for MCF_SDRAMC_SDDS */
#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
/* Bit definitions and macros for MCF_SDRAMC_SDCS */
#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*
* Edge Port Module (EPORT)
m68knommu: remove a lot of unsed definitions for 532x ColdFire There are a lot of unused and uneccessary definitions in the header to support the ColdFire 532x CPU family. Remove the junk. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-17 13:04:42 +08:00
*/
generic GPIO support for the Freescale Coldfire 532x. Add support for the 532x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:10 +08:00
#define MCFEPORT_EPPAR (0xFC094000)
#define MCFEPORT_EPDDR (0xFC094002)
#define MCFEPORT_EPIER (0xFC094003)
#define MCFEPORT_EPDR (0xFC094004)
#define MCFEPORT_EPPDR (0xFC094005)
#define MCFEPORT_EPFR (0xFC094006)
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
m68knommu: platform support for i2c devices on ColdFire SoC These changes based on work by Steven King <sfking@fdwdc.com> to support the i2c hardware modules on ColdFire SoC family devices. This is the per SoC hardware support. Contains a common platform device setup. Each of the SoC family members tends to have some minor local setup required to initialize the module. But all ColdFire family members use the same i2c hardware module. This i2c hardware module is the same as used in the Freescale iMX ARM based family of SoC devices. Steven's original patches were based on using a new and different i2c-coldfire.c driver. But this is not neccessary as we can use the existing Linux i2c-imx.c driver with no change required to it. And this patch is now based on using the existing i2c-imx driver. This patch only contains the ColdFire platform changes. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Tested-by: Angelo Dureghello <angelo@sysam.it>
2014-07-01 00:53:19 +08:00
/*
* I2C Module
*/
#define MCFI2C_BASE0 (0xFc058000)
#define MCFI2C_SIZE0 0x40
[PATCH] m68knommu: ColdFire 532x register definitions Register definitions for the new Freescale 532x Coldfire CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-26 08:33:10 +08:00
/********************************************************************/
m68knommu: create and use a common M53xx ColdFire class of CPUs The current CONFIG_M532x support definitions are actually common to a larger set of version 3 ColdFire CPU types. In the future we want to add support for the 537x family. It is very similar to the 532x internally, and will be able to use most of the same definitions. Create a CONFIG_M53xx option that is enabled to support any of the common 532x and 537x CPU types. Convert the current users of CONFIG_M532x to use CONFIG_M53xx instead. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-11-05 10:01:38 +08:00
#endif /* m53xxsim_h */