2016-06-13 23:10:25 +08:00
|
|
|
* Atmel Quad Serial Peripheral Interface (QSPI)
|
|
|
|
|
|
|
|
Required properties:
|
2019-02-06 01:33:35 +08:00
|
|
|
- compatible: Should be one of the following:
|
|
|
|
- "atmel,sama5d2-qspi"
|
|
|
|
- "microchip,sam9x60-qspi"
|
2016-06-13 23:10:25 +08:00
|
|
|
- reg: Should contain the locations and lengths of the base registers
|
|
|
|
and the mapped memory.
|
|
|
|
- reg-names: Should contain the resource reg names:
|
|
|
|
- qspi_base: configuration register address space
|
|
|
|
- qspi_mmap: memory mapped address space
|
|
|
|
- interrupts: Should contain the interrupt for the device.
|
2019-02-06 01:33:35 +08:00
|
|
|
- clocks: Should reference the peripheral clock and the QSPI system
|
|
|
|
clock if available.
|
|
|
|
- clock-names: Should contain "pclk" for the peripheral clock and "qspick"
|
|
|
|
for the system clock when available.
|
2016-06-13 23:10:25 +08:00
|
|
|
- #address-cells: Should be <1>.
|
|
|
|
- #size-cells: Should be <0>.
|
|
|
|
|
|
|
|
Example:
|
|
|
|
|
|
|
|
spi@f0020000 {
|
|
|
|
compatible = "atmel,sama5d2-qspi";
|
|
|
|
reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
|
|
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
|
|
interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
|
2019-02-06 01:33:27 +08:00
|
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
|
2019-02-06 01:33:30 +08:00
|
|
|
clock-names = "pclk";
|
2016-06-13 23:10:25 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_spi0_default>;
|
|
|
|
|
|
|
|
m25p80@0 {
|
|
|
|
...
|
|
|
|
};
|
|
|
|
};
|