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linux/arch/m68k/include/asm/m523xsim.h

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[PATCH] m68knommu: ColdFire 523x processor register definitions ColdFire 523x processor hardware register definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-09 07:32:14 +08:00
/****************************************************************************/
/*
* m523xsim.h -- ColdFire 523x System Integration Module support.
*
* (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m523xsim_h
#define m523xsim_h
/****************************************************************************/
m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 15:40:37 +08:00
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
[PATCH] m68knommu: ColdFire 523x processor register definitions ColdFire 523x processor hardware register definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-09 07:32:14 +08:00
m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-09 08:12:29 +08:00
#include <asm/m52xxacr.h>
[PATCH] m68knommu: ColdFire 523x processor register definitions ColdFire 523x processor hardware register definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-09 07:32:14 +08:00
/*
* Define the 523x SIM register set addresses.
*/
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 20:17:17 +08:00
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
[PATCH] m68knommu: ColdFire 523x processor register definitions ColdFire 523x processor hardware register definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-09 07:32:14 +08:00
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
m68knommu: move CPU reset code for the 523x ColdFire into its platform code Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-04-30 20:58:35 +08:00
/*
* Reset Controll Unit (relative to IPSBAR).
*/
#define MCF_RCR 0x110000
#define MCF_RSR 0x110001
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
/*
* UART module.
*/
m68knommu: remove use of MBAR value for ColdFire 523x peripheral addressing The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 22:05:29 +08:00
#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 10:50:30 +08:00
m68knommu: remove use of MBAR value for ColdFire 523x peripheral addressing The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 22:05:29 +08:00
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
#define MCFFEC_SIZE 0x800
/*
* GPIO module.
*/
generic GPIO support for the Freescale Coldfire 523x. Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:04 +08:00
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
/*
m68knommu: move ColdFire PIT timer base addresses The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 21:32:35 +08:00
* PIT timer base addresses.
generic GPIO support for the Freescale Coldfire 523x. Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:04 +08:00
*/
m68knommu: move ColdFire PIT timer base addresses The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 21:32:35 +08:00
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
generic GPIO support for the Freescale Coldfire 523x. Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:04 +08:00
m68knommu: move ColdFire PIT timer base addresses The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 21:32:35 +08:00
/*
* EPort
*/
generic GPIO support for the Freescale Coldfire 523x. Add support for the 523x. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 09:11:04 +08:00
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
#define MCFGPIO_PIN_MAX 107
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
m68knommu: Coldfire QSPI platform support Since Grant has added the coldfire-qspi driver to next-spi, here is the platform support for the parts that have qspi hardware. This sets up gpio to do the spi chip select using the default chip select pins; it should be trivial for boards that require different or additional spi chip selects to use other gpios as needed. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-01-23 04:43:03 +08:00
/*
* Pin Assignment
*/
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
[PATCH] m68knommu: ColdFire 523x processor register definitions ColdFire 523x processor hardware register definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-09 07:32:14 +08:00
/****************************************************************************/
#endif /* m523xsim_h */