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linux/arch/c6x/include/asm/cache.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 16:11:33 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
C6X: cache control Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-04 23:11:35 +08:00
/*
* Port on Texas Instruments TMS320C6x architecture
*
C6X: add Lx_CACHE_SHIFT defines C6X currently lacks Lx_CACHE_SHIFT defines which are needed in a few places in the generic kernel. This patch adds _SHIFT defines for the various caches and bases the Lx_CACHE_BYTES defines on them. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-08-15 23:52:01 +08:00
* Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
C6X: cache control Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-04 23:11:35 +08:00
* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
*/
#ifndef _ASM_C6X_CACHE_H
#define _ASM_C6X_CACHE_H
#include <linux/irqflags.h>
c6x: fix build failure caused by cache.h A patch to linux/irqflags.h uncovered a problem with c6x asm/cache.h which causes a build failure: /arch/c6x/include/asm/cache.h:63:20: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘c6x_cache_init’ extern void __init c6x_cache_init(void); The asm/cache.h was relying on linux/irqflags.h to pull in linux/init.h but the recent patch changed that. The c6x header should have included linux/init.h all along. Signed-off-by: Mark Salter <msalter@redhat.com>
2013-11-11 21:28:33 +08:00
#include <linux/init.h>
C6X: cache control Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-04 23:11:35 +08:00
/*
* Cache line size
*/
C6X: add Lx_CACHE_SHIFT defines C6X currently lacks Lx_CACHE_SHIFT defines which are needed in a few places in the generic kernel. This patch adds _SHIFT defines for the various caches and bases the Lx_CACHE_BYTES defines on them. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-08-15 23:52:01 +08:00
#define L1D_CACHE_SHIFT 6
#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT)
#define L1P_CACHE_SHIFT 5
#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT)
#define L2_CACHE_SHIFT 7
#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
C6X: cache control Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-04 23:11:35 +08:00
/*
* L2 used as cache
*/
#define L2MODE_SIZE L2MODE_256K_CACHE
/*
* For practical reasons the L1_CACHE_BYTES defines should not be smaller than
* the L2 line size
*/
C6X: add Lx_CACHE_SHIFT defines C6X currently lacks Lx_CACHE_SHIFT defines which are needed in a few places in the generic kernel. This patch adds _SHIFT defines for the various caches and bases the Lx_CACHE_BYTES defines on them. Signed-off-by: Mark Salter <msalter@redhat.com>
2012-08-15 23:52:01 +08:00
#define L1_CACHE_SHIFT L2_CACHE_SHIFT
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
C6X: cache control Original port to early 2.6 kernel using TI COFF toolchain. Brought up to date by Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-10-04 23:11:35 +08:00
#define L2_CACHE_ALIGN_LOW(x) \
(((x) & ~(L2_CACHE_BYTES - 1)))
#define L2_CACHE_ALIGN_UP(x) \
(((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
#define L2_CACHE_ALIGN_CNT(x) \
(((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
/*
* This is the granularity of hardware cacheability control.
*/
#define CACHEABILITY_ALIGN 0x01000000
/*
* Align a physical address to MAR regions
*/
#define CACHE_REGION_START(v) \
(((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
#define CACHE_REGION_END(v) \
(((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
extern void __init c6x_cache_init(void);
extern void enable_caching(unsigned long start, unsigned long end);
extern void disable_caching(unsigned long start, unsigned long end);
extern void L1_cache_off(void);
extern void L1_cache_on(void);
extern void L1P_cache_global_invalidate(void);
extern void L1D_cache_global_invalidate(void);
extern void L1D_cache_global_writeback(void);
extern void L1D_cache_global_writeback_invalidate(void);
extern void L2_cache_set_mode(unsigned int mode);
extern void L2_cache_global_writeback_invalidate(void);
extern void L2_cache_global_writeback(void);
extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L1D_cache_block_writeback_invalidate(unsigned int start,
unsigned int end);
extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
extern void L2_cache_block_writeback_invalidate(unsigned int start,
unsigned int end);
extern void L2_cache_block_invalidate_nowait(unsigned int start,
unsigned int end);
extern void L2_cache_block_writeback_nowait(unsigned int start,
unsigned int end);
extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
unsigned int end);
#endif /* _ASM_C6X_CACHE_H */