2015-07-14 14:58:12 +08:00
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+Mediatek 65xx/67xx/81xx sysirq
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2014-11-25 16:04:22 +08:00
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Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
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interrupt.
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Required properties:
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- compatible: should be one of:
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2015-12-01 17:14:00 +08:00
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"mediatek,mt8173-sysirq"
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2014-11-25 16:04:22 +08:00
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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2015-07-14 14:58:12 +08:00
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"mediatek,mt6795-sysirq"
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2016-06-29 10:09:32 +08:00
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"mediatek,mt6755-sysirq"
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2015-01-08 14:23:11 +08:00
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"mediatek,mt6592-sysirq"
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2014-11-25 16:04:22 +08:00
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"mediatek,mt6589-sysirq"
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"mediatek,mt6582-sysirq"
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2015-07-14 14:07:08 +08:00
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"mediatek,mt6580-sysirq"
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2014-11-25 16:04:22 +08:00
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"mediatek,mt6577-sysirq"
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2015-10-20 14:34:30 +08:00
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"mediatek,mt2701-sysirq"
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2014-11-25 16:04:22 +08:00
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- interrupt-controller : Identifies the node as an interrupt controller
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2016-03-17 22:47:57 +08:00
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- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
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2014-11-25 16:04:22 +08:00
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- interrupt-parent: phandle of irq parent for sysirq. The parent must
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use the same interrupt-cells format as GIC.
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- reg: Physical base address of the intpol registers and length of memory
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mapped region.
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Example:
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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