linux/arch/s390/kernel/cache.c

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
// SPDX-License-Identifier: GPL-2.0
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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/*
* Extract CPU cache information and expose them via sysfs.
*
* Copyright IBM Corp. 2012
* Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
*/
#include <linux/seq_file.h>
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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#include <linux/cpu.h>
#include <linux/cacheinfo.h>
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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#include <asm/facility.h>
enum {
CACHE_SCOPE_NOTEXISTS,
CACHE_SCOPE_PRIVATE,
CACHE_SCOPE_SHARED,
CACHE_SCOPE_RESERVED,
};
enum {
CTYPE_SEPARATE,
CTYPE_DATA,
CTYPE_INSTRUCTION,
CTYPE_UNIFIED,
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
};
enum {
EXTRACT_TOPOLOGY,
EXTRACT_LINE_SIZE,
EXTRACT_SIZE,
EXTRACT_ASSOCIATIVITY,
};
enum {
CACHE_TI_UNIFIED = 0,
CACHE_TI_DATA = 0,
CACHE_TI_INSTRUCTION,
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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};
struct cache_info {
unsigned char : 4;
unsigned char scope : 2;
unsigned char type : 2;
};
#define CACHE_MAX_LEVEL 8
union cache_topology {
struct cache_info ci[CACHE_MAX_LEVEL];
unsigned long long raw;
};
static const char * const cache_type_string[] = {
"",
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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"Instruction",
"Data",
"",
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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"Unified",
};
static const enum cache_type cache_type_map[] = {
[CTYPE_SEPARATE] = CACHE_TYPE_SEPARATE,
[CTYPE_DATA] = CACHE_TYPE_DATA,
[CTYPE_INSTRUCTION] = CACHE_TYPE_INST,
[CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED,
};
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
void show_cacheinfo(struct seq_file *m)
{
struct cpu_cacheinfo *this_cpu_ci;
struct cacheinfo *cache;
int idx;
if (!test_facility(34))
return;
this_cpu_ci = get_cpu_cacheinfo(cpumask_any(cpu_online_mask));
for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) {
cache = this_cpu_ci->info_list + idx;
seq_printf(m, "cache%-11d: ", idx);
seq_printf(m, "level=%d ", cache->level);
seq_printf(m, "type=%s ", cache_type_string[cache->type]);
seq_printf(m, "scope=%s ",
cache->disable_sysfs ? "Shared" : "Private");
seq_printf(m, "size=%dK ", cache->size >> 10);
seq_printf(m, "line_size=%u ", cache->coherency_line_size);
seq_printf(m, "associativity=%d", cache->ways_of_associativity);
seq_puts(m, "\n");
}
}
static inline enum cache_type get_cache_type(struct cache_info *ci, int level)
{
if (level >= CACHE_MAX_LEVEL)
return CACHE_TYPE_NOCACHE;
ci += level;
if (ci->scope != CACHE_SCOPE_SHARED && ci->scope != CACHE_SCOPE_PRIVATE)
return CACHE_TYPE_NOCACHE;
return cache_type_map[ci->type];
}
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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static inline unsigned long ecag(int ai, int li, int ti)
{
return __ecag(ECAG_CACHE_ATTRIBUTE, ai << 4 | li << 1 | ti);
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
}
static void ci_leaf_init(struct cacheinfo *this_leaf, int private,
enum cache_type type, unsigned int level, int cpu)
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
{
int ti, num_sets;
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
if (type == CACHE_TYPE_INST)
ti = CACHE_TI_INSTRUCTION;
else
ti = CACHE_TI_UNIFIED;
this_leaf->level = level + 1;
this_leaf->type = type;
this_leaf->coherency_line_size = ecag(EXTRACT_LINE_SIZE, level, ti);
this_leaf->ways_of_associativity = ecag(EXTRACT_ASSOCIATIVITY, level, ti);
this_leaf->size = ecag(EXTRACT_SIZE, level, ti);
num_sets = this_leaf->size / this_leaf->coherency_line_size;
num_sets /= this_leaf->ways_of_associativity;
this_leaf->number_of_sets = num_sets;
cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
if (!private)
this_leaf->disable_sysfs = true;
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
}
int init_cache_level(unsigned int cpu)
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
{
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
unsigned int level = 0, leaves = 0;
union cache_topology ct;
enum cache_type ctype;
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
2015-07-27 15:53:49 +08:00
if (!test_facility(34))
return -EOPNOTSUPP;
if (!this_cpu_ci)
return -EINVAL;
ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);
do {
ctype = get_cache_type(&ct.ci[0], level);
if (ctype == CACHE_TYPE_NOCACHE)
break;
/* Separate instruction and data caches */
leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
} while (++level < CACHE_MAX_LEVEL);
this_cpu_ci->num_levels = level;
this_cpu_ci->num_leaves = leaves;
return 0;
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
}
int populate_cache_leaves(unsigned int cpu)
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
{
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
unsigned int level, idx, pvt;
union cache_topology ct;
enum cache_type ctype;
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
if (!test_facility(34))
return -EOPNOTSUPP;
ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);
for (idx = 0, level = 0; level < this_cpu_ci->num_levels &&
idx < this_cpu_ci->num_leaves; idx++, level++) {
if (!this_leaf)
return -EINVAL;
pvt = (ct.ci[level].scope == CACHE_SCOPE_PRIVATE) ? 1 : 0;
ctype = get_cache_type(&ct.ci[0], level);
if (ctype == CACHE_TYPE_SEPARATE) {
ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_DATA, level, cpu);
ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_INST, level, cpu);
} else {
ci_leaf_init(this_leaf++, pvt, ctype, level, cpu);
}
s390/cache: expose cpu cache topology via sysfs Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-08-23 22:31:13 +08:00
}
return 0;
}