License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2009-06-12 13:11:17 +08:00
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#ifndef _M68K_DMA_H
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#define _M68K_DMA_H 1
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#ifdef CONFIG_COLDFIRE
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/*
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* ColdFire DMA Model:
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* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
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* address mode emits a source address, and expects that the device will either
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* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
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* the device will place data on the correct byte(s) of the data bus, as the
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* memory transactions are always 32 bits. This implies that only 32 bit
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* devices will find single mode transfers useful. Dual address DMA mode
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* performs two cycles: source read and destination write. ColdFire will
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* align the data so that the device will always get the correct bytes, thus
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* is useful for 8 and 16 bit devices. This is the mode that is supported
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* below.
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*
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* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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2016-05-21 19:57:20 +08:00
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* AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
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2009-06-12 13:11:17 +08:00
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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* APR/18/2002 : added proper support for MCF5272 DMA controller.
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* Arthur Shipkowski (art@videon-central.com)
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*/
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfdma.h>
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/*
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* Set number of channels of DMA on ColdFire for different implementations.
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*/
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#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
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2012-06-05 23:23:08 +08:00
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defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
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defined(CONFIG_M528x) || defined(CONFIG_M525x)
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2009-06-12 13:11:17 +08:00
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#define MAX_M68K_DMA_CHANNELS 4
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#elif defined(CONFIG_M5272)
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#define MAX_M68K_DMA_CHANNELS 1
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2012-11-05 10:01:38 +08:00
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#elif defined(CONFIG_M53xx)
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2009-06-12 13:11:17 +08:00
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#define MAX_M68K_DMA_CHANNELS 0
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2009-01-16 19:58:10 +08:00
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#else
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2009-06-12 13:11:17 +08:00
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#define MAX_M68K_DMA_CHANNELS 2
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2009-01-16 19:58:10 +08:00
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#endif
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2009-06-12 13:11:17 +08:00
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extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
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extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
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#if !defined(CONFIG_M5272)
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#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
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#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
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#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
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#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
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/* I/O to memory, 8 bits, mode */
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#define DMA_MODE_READ 0
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/* memory to I/O, 8 bits, mode */
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#define DMA_MODE_WRITE 1
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/* I/O to memory, 16 bits, mode */
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#define DMA_MODE_READ_WORD 2
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/* memory to I/O, 16 bits, mode */
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#define DMA_MODE_WRITE_WORD 3
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/* I/O to memory, 32 bits, mode */
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#define DMA_MODE_READ_LONG 4
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/* memory to I/O, 32 bits, mode */
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#define DMA_MODE_WRITE_LONG 5
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/* I/O to memory, 8 bits, single-address-mode */
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#define DMA_MODE_READ_SINGLE 8
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/* memory to I/O, 8 bits, single-address-mode */
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#define DMA_MODE_WRITE_SINGLE 9
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/* I/O to memory, 16 bits, single-address-mode */
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#define DMA_MODE_READ_WORD_SINGLE 10
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/* memory to I/O, 16 bits, single-address-mode */
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#define DMA_MODE_WRITE_WORD_SINGLE 11
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/* I/O to memory, 32 bits, single-address-mode */
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#define DMA_MODE_READ_LONG_SINGLE 12
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/* memory to I/O, 32 bits, single-address-mode */
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#define DMA_MODE_WRITE_LONG_SINGLE 13
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#else /* CONFIG_M5272 is defined */
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/* Source static-address mode */
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#define DMA_MODE_SRC_SA_BIT 0x01
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/* Two bits to select between all four modes */
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#define DMA_MODE_SSIZE_MASK 0x06
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/* Offset to shift bits in */
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#define DMA_MODE_SSIZE_OFF 0x01
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/* Destination static-address mode */
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#define DMA_MODE_DES_SA_BIT 0x10
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/* Two bits to select between all four modes */
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#define DMA_MODE_DSIZE_MASK 0x60
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/* Offset to shift bits in */
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#define DMA_MODE_DSIZE_OFF 0x05
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/* Size modifiers */
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#define DMA_MODE_SIZE_LONG 0x00
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#define DMA_MODE_SIZE_BYTE 0x01
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#define DMA_MODE_SIZE_WORD 0x02
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#define DMA_MODE_SIZE_LINE 0x03
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/*
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* Aliases to help speed quick ports; these may be suboptimal, however. They
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* do not include the SINGLE mode modifiers since the MCF5272 does not have a
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* mode where the device is in control of its addressing.
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*/
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/* I/O to memory, 8 bits, mode */
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#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 8 bits, mode */
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#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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/* I/O to memory, 16 bits, mode */
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#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 16 bits, mode */
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#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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/* I/O to memory, 32 bits, mode */
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#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
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/* memory to I/O, 32 bits, mode */
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#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
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#endif /* !defined(CONFIG_M5272) */
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#if !defined(CONFIG_M5272)
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("enable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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volatile unsigned short *dmawp;
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volatile unsigned char *dmapb;
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#ifdef DMA_DEBUG
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printk("disable_dma(dmanr=%d)\n", dmanr);
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#endif
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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dmapb = (unsigned char *) dma_base_addr[dmanr];
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/* Turn off external requests, and stop any DMA in progress */
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dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
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dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
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}
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/*
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* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while interrupts are disabled! ---
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*
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* This is a NOP for ColdFire. Provide a stub for compatibility.
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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volatile unsigned char *dmabp;
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volatile unsigned short *dmawp;
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#ifdef DMA_DEBUG
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printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
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#endif
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dmabp = (unsigned char *) dma_base_addr[dmanr];
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dmawp = (unsigned short *) dma_base_addr[dmanr];
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2009-08-05 12:02:48 +08:00
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/* Clear config errors */
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2009-06-12 13:11:17 +08:00
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dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
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2009-08-05 12:02:48 +08:00
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/* Set command register */
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2009-06-12 13:11:17 +08:00
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dmawp[MCFDMA_DCR] =
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2009-08-05 12:02:48 +08:00
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MCFDMA_DCR_INT | /* Enable completion irq */
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MCFDMA_DCR_CS | /* Force one xfer per request */
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MCFDMA_DCR_AA | /* Enable auto alignment */
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/* single-address-mode */
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2009-06-12 13:11:17 +08:00
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((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
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2009-08-05 12:02:48 +08:00
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/* sets s_rw (-> r/w) high if Memory to I/0 */
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2009-06-12 13:11:17 +08:00
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((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
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2009-08-05 12:02:48 +08:00
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/* Memory to I/O or I/O to Memory */
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2009-06-12 13:11:17 +08:00
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((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
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2009-08-05 12:02:48 +08:00
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/* 32 bit, 16 bit or 8 bit transfers */
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2009-06-12 13:11:17 +08:00
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((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
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((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
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MCFDMA_DCR_SSIZE_BYTE)) |
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((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
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((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
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MCFDMA_DCR_DSIZE_BYTE));
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#ifdef DEBUG_DMA
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printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
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dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
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(int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
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#endif
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}
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/* Set transfer address for specific DMA channel */
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|
|
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned short *dmawp;
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmawp = (unsigned short *) dma_base_addr[dmanr];
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Determine which address registers are used for memory/device accesses */
|
2009-06-12 13:11:17 +08:00
|
|
|
if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Source incrementing, must be memory */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_SAR] = a;
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Set dest address, must be device */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
|
|
|
|
|
} else {
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Destination incrementing, must be memory */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DAR] = a;
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Set source address, must be device */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef DEBUG_DMA
|
|
|
|
|
printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
|
|
|
|
|
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
|
|
|
|
|
(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
|
|
|
|
|
(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Specific for Coldfire - sets device address.
|
|
|
|
|
* Should be called after the mode set call, and before set DMA address.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
|
|
|
|
|
{
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dma_device_address[dmanr] = a;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* NOTE 2: "count" represents _bytes_.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned short *dmawp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmawp = (unsigned short *) dma_base_addr[dmanr];
|
|
|
|
|
dmawp[MCFDMA_BCR] = (unsigned short)count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Get DMA residue count. After a DMA transfer, this
|
|
|
|
|
* should return zero. Reading this while a DMA transfer is
|
|
|
|
|
* still in progress will return unpredictable results.
|
|
|
|
|
* Otherwise, it returns the number of _bytes_ left to transfer.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ int get_dma_residue(unsigned int dmanr)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned short *dmawp;
|
|
|
|
|
unsigned short count;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("get_dma_residue(dmanr=%d)\n", dmanr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmawp = (unsigned short *) dma_base_addr[dmanr];
|
|
|
|
|
count = dmawp[MCFDMA_BCR];
|
|
|
|
|
return((int) count);
|
|
|
|
|
}
|
|
|
|
|
#else /* CONFIG_M5272 is defined */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The MCF5272 DMA controller is very different than the controller defined above
|
|
|
|
|
* in terms of register mapping. For instance, with the exception of the 16-bit
|
|
|
|
|
* interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
|
|
|
|
|
*
|
|
|
|
|
* The big difference, however, is the lack of device-requested DMA. All modes
|
|
|
|
|
* are dual address transfer, and there is no 'device' setup or direction bit.
|
|
|
|
|
* You can DMA between a device and memory, between memory and memory, or even between
|
|
|
|
|
* two devices directly, with any combination of incrementing and non-incrementing
|
|
|
|
|
* addresses you choose. This puts a crimp in distinguishing between the 'device
|
|
|
|
|
* address' set up by set_dma_device_addr.
|
|
|
|
|
*
|
|
|
|
|
* Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
|
|
|
|
|
* which will act exactly as above in -- it will look to see if the source is set to
|
|
|
|
|
* autoincrement, and if so it will make the source use the set_dma_addr value and the
|
|
|
|
|
* destination the set_dma_device_addr value. Otherwise the source will be set to the
|
|
|
|
|
* set_dma_device_addr value and the destination will get the set_dma_addr value.
|
|
|
|
|
*
|
|
|
|
|
* The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
|
|
|
|
|
* and make it explicit. Depending on what you're doing, one of these two should work
|
|
|
|
|
* for you, but don't mix them in the same transfer setup.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* enable/disable a specific DMA channel */
|
|
|
|
|
static __inline__ void enable_dma(unsigned int dmanr)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("enable_dma(dmanr=%d)\n", dmanr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ void disable_dma(unsigned int dmanr)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("disable_dma(dmanr=%d)\n", dmanr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
|
|
|
|
|
/* Turn off external requests, and stop any DMA in progress */
|
|
|
|
|
dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
|
|
|
|
|
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Clear the 'DMA Pointer Flip Flop'.
|
|
|
|
|
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
|
|
|
|
|
* Use this once to initialize the FF to a known state.
|
|
|
|
|
* After that, keep track of it. :-)
|
|
|
|
|
* --- In order to do that, the DMA routines below should ---
|
|
|
|
|
* --- only be used while interrupts are disabled! ---
|
|
|
|
|
*
|
|
|
|
|
* This is a NOP for ColdFire. Provide a stub for compatibility.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ void clear_dma_ff(unsigned int dmanr)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* set mode (above) for a specific DMA channel */
|
|
|
|
|
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
volatile unsigned short *dmawp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
|
|
|
|
|
#endif
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
dmawp = (unsigned short *) dma_base_addr[dmanr];
|
|
|
|
|
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Clear config errors */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
|
|
|
|
|
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Set command register */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DMR] =
|
2009-08-05 12:02:48 +08:00
|
|
|
MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
|
|
|
|
|
MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
|
|
|
|
|
MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
|
|
|
|
|
/* source static-address-mode */
|
2009-06-12 13:11:17 +08:00
|
|
|
((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
|
2009-08-05 12:02:48 +08:00
|
|
|
/* dest static-address-mode */
|
2009-06-12 13:11:17 +08:00
|
|
|
((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
|
2009-08-05 12:02:48 +08:00
|
|
|
/* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
|
2009-06-12 13:11:17 +08:00
|
|
|
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
|
|
|
|
|
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
|
|
|
|
|
|
|
|
|
|
dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
|
|
|
|
|
|
|
|
|
|
#ifdef DEBUG_DMA
|
|
|
|
|
printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
|
2018-06-22 04:30:53 +08:00
|
|
|
dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
|
2009-06-12 13:11:17 +08:00
|
|
|
(int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set transfer address for specific DMA channel */
|
|
|
|
|
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Determine which address registers are used for memory/device accesses */
|
2009-06-12 13:11:17 +08:00
|
|
|
if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Source incrementing, must be memory */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DSAR] = a;
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Set dest address, must be device */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
|
|
|
|
|
} else {
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Destination incrementing, must be memory */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DDAR] = a;
|
2009-08-05 12:02:48 +08:00
|
|
|
/* Set source address, must be device */
|
2009-06-12 13:11:17 +08:00
|
|
|
dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef DEBUG_DMA
|
|
|
|
|
printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
|
2018-06-22 04:30:53 +08:00
|
|
|
__FILE__, __LINE__, dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
|
2009-06-12 13:11:17 +08:00
|
|
|
(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
|
|
|
|
|
(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Specific for Coldfire - sets device address.
|
|
|
|
|
* Should be called after the mode set call, and before set DMA address.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
|
|
|
|
|
{
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dma_device_address[dmanr] = a;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* NOTE 2: "count" represents _bytes_.
|
|
|
|
|
*
|
|
|
|
|
* NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
dmalp[MCFDMA_DBCR] = count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Get DMA residue count. After a DMA transfer, this
|
|
|
|
|
* should return zero. Reading this while a DMA transfer is
|
|
|
|
|
* still in progress will return unpredictable results.
|
|
|
|
|
* Otherwise, it returns the number of _bytes_ left to transfer.
|
|
|
|
|
*/
|
|
|
|
|
static __inline__ int get_dma_residue(unsigned int dmanr)
|
|
|
|
|
{
|
|
|
|
|
volatile unsigned int *dmalp;
|
|
|
|
|
unsigned int count;
|
|
|
|
|
|
|
|
|
|
#ifdef DMA_DEBUG
|
|
|
|
|
printk("get_dma_residue(dmanr=%d)\n", dmanr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
dmalp = (unsigned int *) dma_base_addr[dmanr];
|
|
|
|
|
count = dmalp[MCFDMA_DBCR];
|
|
|
|
|
return(count);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* !defined(CONFIG_M5272) */
|
|
|
|
|
#endif /* CONFIG_COLDFIRE */
|
|
|
|
|
|
|
|
|
|
/* it's useless on the m68k, but unfortunately needed by the new
|
|
|
|
|
bootmem allocator (but this should do it for this) */
|
|
|
|
|
#define MAX_DMA_ADDRESS PAGE_OFFSET
|
|
|
|
|
|
|
|
|
|
#define MAX_DMA_CHANNELS 8
|
|
|
|
|
|
|
|
|
|
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
|
|
|
|
|
extern void free_dma(unsigned int dmanr); /* release it again */
|
|
|
|
|
|
2011-11-28 14:32:49 +08:00
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
extern int isa_dma_bridge_buggy;
|
|
|
|
|
#else
|
2009-06-12 13:11:17 +08:00
|
|
|
#define isa_dma_bridge_buggy (0)
|
2011-11-28 14:32:49 +08:00
|
|
|
#endif
|
2009-06-12 13:11:17 +08:00
|
|
|
|
|
|
|
|
#endif /* _M68K_DMA_H */
|