2012-07-11 08:26:48 +08:00
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/*
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* Paravirt target for a generic QEMU e500 machine
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*
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* This is intended to be a flexible device-tree-driven platform, not fixed
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* to a particular piece of hardware or a particular spec of virtual hardware,
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* beyond the assumption of an e500-family CPU. Some things are still hardcoded
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* here, such as MPIC, but this is a limitation of the current code rather than
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* an interface contract with QEMU.
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/of_fdt.h>
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#include <asm/machdep.h>
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2014-08-09 07:40:45 +08:00
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#include <asm/pgtable.h>
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2012-07-11 08:26:48 +08:00
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#include <asm/time.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "smp.h"
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#include "mpc85xx.h"
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void __init qemu_e500_pic_init(void)
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{
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struct mpic *mpic;
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2013-01-22 09:56:43 +08:00
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unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
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MPIC_ENABLE_COREINT;
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2012-07-11 08:26:48 +08:00
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2013-01-22 09:56:43 +08:00
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mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
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2012-07-11 08:26:48 +08:00
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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static void __init qemu_e500_setup_arch(void)
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{
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ppc_md.progress("qemu_e500_setup_arch()", 0);
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2012-08-28 15:44:08 +08:00
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fsl_pci_assign_primary();
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2012-08-03 18:14:10 +08:00
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swiotlb_detect_4g();
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2014-08-09 07:40:45 +08:00
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#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
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/*
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* Inbound windows don't cover the full lower 4 GiB
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* due to conflicts with PCICSRBAR and outbound windows,
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* so limit the DMA32 zone to 2 GiB, to allow consistent
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* allocations to succeed.
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*/
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limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
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#endif
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2012-07-11 08:26:48 +08:00
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mpc85xx_smp_init();
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init qemu_e500_probe(void)
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{
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2016-07-05 13:04:05 +08:00
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return !!of_machine_is_compatible("fsl,qemu-e500");
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2012-07-11 08:26:48 +08:00
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}
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2012-08-28 15:44:08 +08:00
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machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
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2012-07-11 08:26:48 +08:00
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define_machine(qemu_e500) {
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.name = "QEMU e500",
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.probe = qemu_e500_probe,
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.setup_arch = qemu_e500_setup_arch,
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.init_IRQ = qemu_e500_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-03-20 11:19:37 +08:00
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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2012-07-11 08:26:48 +08:00
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#endif
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2013-01-22 09:56:43 +08:00
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.get_irq = mpic_get_coreint_irq,
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2012-07-11 08:26:48 +08:00
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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