2008-10-02 13:27:57 +08:00
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/***************************************************************************
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*
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* Copyright (C) 2007-2008 SMSC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*****************************************************************************/
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#include <linux/module.h>
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#include <linux/kmod.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/usb.h>
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2012-10-26 11:43:56 +08:00
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#include <linux/bitrev.h>
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#include <linux/crc16.h>
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2008-10-02 13:27:57 +08:00
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#include <linux/crc32.h>
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#include <linux/usb/usbnet.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2008-10-02 13:27:57 +08:00
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#include "smsc95xx.h"
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#define SMSC_CHIPNAME "smsc95xx"
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2008-11-20 20:19:21 +08:00
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#define SMSC_DRIVER_VERSION "1.0.4"
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2008-10-02 13:27:57 +08:00
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#define HS_USB_PKT_SIZE (512)
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#define FS_USB_PKT_SIZE (64)
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#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
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#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
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#define DEFAULT_BULK_IN_DELAY (0x00002000)
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#define MAX_SINGLE_PACKET_SIZE (2048)
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#define LAN95XX_EEPROM_MAGIC (0x9500)
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#define EEPROM_MAC_OFFSET (0x01)
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2008-11-20 20:19:21 +08:00
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#define DEFAULT_TX_CSUM_ENABLE (true)
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2008-10-02 13:27:57 +08:00
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#define DEFAULT_RX_CSUM_ENABLE (true)
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#define SMSC95XX_INTERNAL_PHY_ID (1)
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#define SMSC95XX_TX_OVERHEAD (8)
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2008-11-20 20:19:21 +08:00
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#define SMSC95XX_TX_OVERHEAD_CSUM (12)
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2012-10-26 11:43:56 +08:00
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#define SUPPORTED_WAKE (WAKE_UCAST | WAKE_BCAST | \
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WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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#define check_warn(ret, fmt, args...) \
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({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
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#define check_warn_return(ret, fmt, args...) \
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({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
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#define check_warn_goto_done(ret, fmt, args...) \
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({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
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2008-10-02 13:27:57 +08:00
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struct smsc95xx_priv {
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u32 mac_cr;
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2011-03-18 11:53:58 +08:00
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u32 hash_hi;
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u32 hash_lo;
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2012-09-28 08:07:12 +08:00
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u32 wolopts;
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2008-10-02 13:27:57 +08:00
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spinlock_t mac_cr_lock;
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2012-10-26 11:43:56 +08:00
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int wuff_filter_count;
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2008-10-02 13:27:57 +08:00
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};
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2011-12-19 22:08:01 +08:00
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static bool turbo_mode = true;
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2008-10-02 13:27:57 +08:00
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module_param(turbo_mode, bool, 0644);
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MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
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2012-11-06 12:53:07 +08:00
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static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
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u32 *data, int in_pm)
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2008-10-02 13:27:57 +08:00
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{
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2012-10-25 03:47:04 +08:00
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u32 buf;
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2008-10-02 13:27:57 +08:00
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int ret;
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2012-11-06 12:53:07 +08:00
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int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
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2008-10-02 13:27:57 +08:00
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BUG_ON(!dev);
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2012-11-06 12:53:07 +08:00
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if (!in_pm)
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fn = usbnet_read_cmd;
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else
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fn = usbnet_read_cmd_nopm;
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ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
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| USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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0, index, &buf, 4);
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2008-10-02 13:27:57 +08:00
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if (unlikely(ret < 0))
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2012-11-06 12:53:07 +08:00
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netdev_warn(dev->net,
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"Failed to read reg index 0x%08x: %d", index, ret);
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2008-10-02 13:27:57 +08:00
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2012-10-25 03:47:04 +08:00
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le32_to_cpus(&buf);
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*data = buf;
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2008-10-02 13:27:57 +08:00
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return ret;
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}
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2012-11-06 12:53:07 +08:00
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static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
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u32 data, int in_pm)
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2008-10-02 13:27:57 +08:00
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{
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2012-10-25 03:47:04 +08:00
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u32 buf;
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2008-10-02 13:27:57 +08:00
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int ret;
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2012-11-06 12:53:07 +08:00
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int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
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2008-10-02 13:27:57 +08:00
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BUG_ON(!dev);
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2012-11-06 12:53:07 +08:00
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if (!in_pm)
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fn = usbnet_write_cmd;
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else
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fn = usbnet_write_cmd_nopm;
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2012-10-25 03:47:04 +08:00
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buf = data;
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cpu_to_le32s(&buf);
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2008-10-02 13:27:57 +08:00
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2012-11-06 12:53:07 +08:00
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ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
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| USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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0, index, &buf, 4);
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2008-10-02 13:27:57 +08:00
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if (unlikely(ret < 0))
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2012-11-06 12:53:07 +08:00
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netdev_warn(dev->net,
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"Failed to write reg index 0x%08x: %d", index, ret);
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2008-10-02 13:27:57 +08:00
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return ret;
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}
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2012-11-06 12:53:07 +08:00
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static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
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u32 *data)
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{
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return __smsc95xx_read_reg(dev, index, data, 1);
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}
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static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
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u32 data)
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{
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return __smsc95xx_write_reg(dev, index, data, 1);
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}
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static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
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u32 *data)
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{
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return __smsc95xx_read_reg(dev, index, data, 0);
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}
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static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
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u32 data)
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{
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return __smsc95xx_write_reg(dev, index, data, 0);
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}
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2012-09-28 08:07:12 +08:00
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static int smsc95xx_set_feature(struct usbnet *dev, u32 feature)
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{
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if (WARN_ON_ONCE(!dev))
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return -EINVAL;
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2012-11-06 12:53:07 +08:00
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return usbnet_write_cmd_nopm(dev, USB_REQ_SET_FEATURE,
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USB_RECIP_DEVICE, feature, 0,
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NULL, 0);
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2012-09-28 08:07:12 +08:00
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}
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static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature)
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{
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if (WARN_ON_ONCE(!dev))
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return -EINVAL;
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2012-11-06 12:53:07 +08:00
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return usbnet_write_cmd_nopm(dev, USB_REQ_CLEAR_FEATURE,
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USB_RECIP_DEVICE, feature,
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0, NULL, 0);
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2012-09-28 08:07:12 +08:00
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}
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2008-10-02 13:27:57 +08:00
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/* Loop until the read is completed with timeout
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* called with phy_mutex held */
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2012-09-28 08:07:09 +08:00
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static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev)
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2008-10-02 13:27:57 +08:00
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{
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unsigned long start_time = jiffies;
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u32 val;
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2012-09-28 08:07:09 +08:00
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int ret;
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2008-10-02 13:27:57 +08:00
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do {
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_read_reg(dev, MII_ADDR, &val);
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check_warn_return(ret, "Error reading MII_ACCESS");
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2008-10-02 13:27:57 +08:00
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if (!(val & MII_BUSY_))
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return 0;
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} while (!time_after(jiffies, start_time + HZ));
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return -EIO;
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}
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static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
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{
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struct usbnet *dev = netdev_priv(netdev);
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u32 val, addr;
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2012-09-28 08:07:09 +08:00
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int ret;
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2008-10-02 13:27:57 +08:00
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mutex_lock(&dev->phy_mutex);
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/* confirm MII not busy */
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_phy_wait_not_busy(dev);
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check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read");
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2008-10-02 13:27:57 +08:00
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/* set the address, index & direction (read from PHY) */
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phy_id &= dev->mii.phy_id_mask;
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idx &= dev->mii.reg_num_mask;
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2012-11-06 08:08:53 +08:00
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addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
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check_warn_goto_done(ret, "Error writing MII_ADDR");
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_phy_wait_not_busy(dev);
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check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx);
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_read_reg(dev, MII_DATA, &val);
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check_warn_goto_done(ret, "Error reading MII_DATA");
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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ret = (u16)(val & 0xFFFF);
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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done:
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mutex_unlock(&dev->phy_mutex);
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return ret;
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2008-10-02 13:27:57 +08:00
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}
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static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
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int regval)
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{
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struct usbnet *dev = netdev_priv(netdev);
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u32 val, addr;
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2012-09-28 08:07:09 +08:00
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int ret;
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2008-10-02 13:27:57 +08:00
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mutex_lock(&dev->phy_mutex);
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/* confirm MII not busy */
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_phy_wait_not_busy(dev);
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check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write");
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2008-10-02 13:27:57 +08:00
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val = regval;
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_write_reg(dev, MII_DATA, val);
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check_warn_goto_done(ret, "Error writing MII_DATA");
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2008-10-02 13:27:57 +08:00
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/* set the address, index & direction (write to PHY) */
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phy_id &= dev->mii.phy_id_mask;
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idx &= dev->mii.reg_num_mask;
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2012-11-06 08:08:53 +08:00
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addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
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check_warn_goto_done(ret, "Error writing MII_ADDR");
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2008-10-02 13:27:57 +08:00
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2012-09-28 08:07:09 +08:00
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ret = smsc95xx_phy_wait_not_busy(dev);
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|
|
check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
done:
|
2008-10-02 13:27:57 +08:00
|
|
|
mutex_unlock(&dev->phy_mutex);
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
|
|
|
unsigned long start_time = jiffies;
|
|
|
|
u32 val;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
do {
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
|
|
|
|
check_warn_return(ret, "Error reading E2P_CMD");
|
2008-10-02 13:27:57 +08:00
|
|
|
if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
|
|
|
|
break;
|
|
|
|
udelay(40);
|
|
|
|
} while (!time_after(jiffies, start_time + HZ));
|
|
|
|
|
|
|
|
if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "EEPROM read operation timeout\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
|
|
|
unsigned long start_time = jiffies;
|
|
|
|
u32 val;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
do {
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
|
|
|
|
check_warn_return(ret, "Error reading E2P_CMD");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (!(val & E2P_CMD_BUSY_))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
udelay(40);
|
|
|
|
} while (!time_after(jiffies, start_time + HZ));
|
|
|
|
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "EEPROM is busy\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
|
|
|
|
u8 *data)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
BUG_ON(!dev);
|
|
|
|
BUG_ON(!data);
|
|
|
|
|
|
|
|
ret = smsc95xx_eeprom_confirm_not_busy(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
|
|
|
val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
|
|
|
|
check_warn_return(ret, "Error writing E2P_CMD");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_wait_eeprom(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
|
|
|
|
check_warn_return(ret, "Error reading E2P_DATA");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
data[i] = val & 0xFF;
|
|
|
|
offset++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
|
|
|
|
u8 *data)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
BUG_ON(!dev);
|
|
|
|
BUG_ON(!data);
|
|
|
|
|
|
|
|
ret = smsc95xx_eeprom_confirm_not_busy(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Issue write/erase enable command */
|
|
|
|
val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
|
|
|
|
check_warn_return(ret, "Error writing E2P_DATA");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_wait_eeprom(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
|
|
|
|
|
|
|
/* Fill data register */
|
|
|
|
val = data[i];
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, E2P_DATA, val);
|
|
|
|
check_warn_return(ret, "Error writing E2P_DATA");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* Send "write" command */
|
|
|
|
val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
|
|
|
|
check_warn_return(ret, "Error writing E2P_CMD");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_wait_eeprom(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
offset++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
|
|
|
|
u32 *data)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
2008-10-10 05:34:47 +08:00
|
|
|
const u16 size = 4;
|
2012-10-25 03:47:04 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-10-25 03:47:04 +08:00
|
|
|
ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
|
|
|
|
USB_DIR_OUT | USB_TYPE_VENDOR |
|
|
|
|
USB_RECIP_DEVICE,
|
|
|
|
0, index, data, size);
|
|
|
|
if (ret < 0)
|
|
|
|
netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* returns hash bit number for given MAC address
|
|
|
|
* example:
|
|
|
|
* 01 00 5E 00 00 01 -> returns bit number 31 */
|
|
|
|
static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
|
|
|
|
{
|
|
|
|
return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smsc95xx_set_multicast(struct net_device *netdev)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
unsigned long flags;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2011-03-18 11:53:58 +08:00
|
|
|
pdata->hash_hi = 0;
|
|
|
|
pdata->hash_lo = 0;
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
|
|
|
|
|
|
|
|
if (dev->net->flags & IFF_PROMISC) {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
pdata->mac_cr |= MAC_CR_PRMS_;
|
|
|
|
pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
|
|
|
|
} else if (dev->net->flags & IFF_ALLMULTI) {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
pdata->mac_cr |= MAC_CR_MCPAS_;
|
|
|
|
pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
|
2010-02-08 12:30:35 +08:00
|
|
|
} else if (!netdev_mc_empty(dev->net)) {
|
2010-04-02 05:22:57 +08:00
|
|
|
struct netdev_hw_addr *ha;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
pdata->mac_cr |= MAC_CR_HPFILT_;
|
|
|
|
pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
|
|
|
|
|
2010-04-02 05:22:57 +08:00
|
|
|
netdev_for_each_mc_addr(ha, netdev) {
|
|
|
|
u32 bitnum = smsc95xx_hash(ha->addr);
|
2010-02-18 12:02:26 +08:00
|
|
|
u32 mask = 0x01 << (bitnum & 0x1F);
|
|
|
|
if (bitnum & 0x20)
|
2011-03-18 11:53:58 +08:00
|
|
|
pdata->hash_hi |= mask;
|
2010-02-18 12:02:26 +08:00
|
|
|
else
|
2011-03-18 11:53:58 +08:00
|
|
|
pdata->hash_lo |= mask;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
|
2011-03-18 11:53:58 +08:00
|
|
|
pdata->hash_hi, pdata->hash_lo);
|
2008-10-02 13:27:57 +08:00
|
|
|
} else {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, drv, dev->net, "receive own packets only\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
pdata->mac_cr &=
|
|
|
|
~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
|
|
|
|
|
|
|
|
/* Initiate async writes, as we can't wait for completion here */
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi);
|
|
|
|
check_warn(ret, "failed to initiate async write to HASHH");
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo);
|
|
|
|
check_warn(ret, "failed to initiate async write to HASHL");
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
|
|
|
|
check_warn(ret, "failed to initiate async write to MAC_CR");
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
|
|
|
|
u16 lcladv, u16 rmtadv)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
|
|
|
u32 flow, afc_cfg = 0;
|
|
|
|
|
|
|
|
int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Error reading AFC_CFG");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (duplex == DUPLEX_FULL) {
|
2008-12-16 18:00:48 +08:00
|
|
|
u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (cap & FLOW_CTRL_RX)
|
|
|
|
flow = 0xFFFF0002;
|
|
|
|
else
|
|
|
|
flow = 0;
|
|
|
|
|
|
|
|
if (cap & FLOW_CTRL_TX)
|
|
|
|
afc_cfg |= 0xF;
|
|
|
|
else
|
|
|
|
afc_cfg &= ~0xF;
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
|
2010-02-17 18:30:23 +08:00
|
|
|
cap & FLOW_CTRL_RX ? "enabled" : "disabled",
|
|
|
|
cap & FLOW_CTRL_TX ? "enabled" : "disabled");
|
2008-10-02 13:27:57 +08:00
|
|
|
} else {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, link, dev->net, "half duplex\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
flow = 0;
|
|
|
|
afc_cfg |= 0xF;
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, FLOW, flow);
|
|
|
|
check_warn_return(ret, "Error writing FLOW");
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
|
|
|
|
check_warn_return(ret, "Error writing AFC_CFG");
|
|
|
|
|
|
|
|
return 0;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_link_reset(struct usbnet *dev)
|
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
struct mii_if_info *mii = &dev->mii;
|
2011-04-28 02:32:38 +08:00
|
|
|
struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
|
2008-10-02 13:27:57 +08:00
|
|
|
unsigned long flags;
|
|
|
|
u16 lcladv, rmtadv;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* clear interrupt status */
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
|
|
|
|
check_warn_return(ret, "Error reading PHY_INT_SRC");
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
|
|
|
|
check_warn_return(ret, "Error writing INT_STS");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
mii_check_media(mii, 1, 1);
|
|
|
|
mii_ethtool_gset(&dev->mii, &ecmd);
|
|
|
|
lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
|
|
|
|
rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
|
|
|
|
|
2011-04-28 02:32:38 +08:00
|
|
|
netif_dbg(dev, link, dev->net,
|
|
|
|
"speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
|
|
|
|
ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
|
|
|
|
if (ecmd.duplex != DUPLEX_FULL) {
|
|
|
|
pdata->mac_cr &= ~MAC_CR_FDPX_;
|
|
|
|
pdata->mac_cr |= MAC_CR_RCVOWN_;
|
|
|
|
} else {
|
|
|
|
pdata->mac_cr &= ~MAC_CR_RCVOWN_;
|
|
|
|
pdata->mac_cr |= MAC_CR_FDPX_;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
|
|
|
|
check_warn_return(ret, "Error writing MAC_CR");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
|
|
|
|
check_warn_return(ret, "Error updating PHY flow control");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
|
|
|
|
{
|
|
|
|
u32 intdata;
|
|
|
|
|
|
|
|
if (urb->actual_length != 4) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "unexpected urb length %d\n",
|
|
|
|
urb->actual_length);
|
2008-10-02 13:27:57 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(&intdata, urb->transfer_buffer, 4);
|
2008-10-10 05:34:47 +08:00
|
|
|
le32_to_cpus(&intdata);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (intdata & INT_ENP_PHY_INT_)
|
|
|
|
usbnet_defer_kevent(dev, EVENT_LINK_RESET);
|
|
|
|
else
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
|
|
|
|
intdata);
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
2008-11-20 20:19:21 +08:00
|
|
|
/* Enable or disable Tx & Rx checksum offload engines */
|
2011-11-15 23:29:55 +08:00
|
|
|
static int smsc95xx_set_features(struct net_device *netdev,
|
|
|
|
netdev_features_t features)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
2011-04-02 11:56:23 +08:00
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
2008-10-02 13:27:57 +08:00
|
|
|
u32 read_buf;
|
2011-04-02 11:56:23 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read COE_CR: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2011-04-02 11:56:23 +08:00
|
|
|
if (features & NETIF_F_HW_CSUM)
|
2008-11-20 20:19:21 +08:00
|
|
|
read_buf |= Tx_COE_EN_;
|
|
|
|
else
|
|
|
|
read_buf &= ~Tx_COE_EN_;
|
|
|
|
|
2011-04-02 11:56:23 +08:00
|
|
|
if (features & NETIF_F_RXCSUM)
|
2008-10-02 13:27:57 +08:00
|
|
|
read_buf |= Rx_COE_EN_;
|
|
|
|
else
|
|
|
|
read_buf &= ~Rx_COE_EN_;
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write COE_CR: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
|
|
|
|
{
|
|
|
|
return MAX_EEPROM_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
|
|
|
|
struct ethtool_eeprom *ee, u8 *data)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
|
|
|
|
|
|
|
ee->magic = LAN95XX_EEPROM_MAGIC;
|
|
|
|
|
|
|
|
return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
|
|
|
|
struct ethtool_eeprom *ee, u8 *data)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
|
|
|
|
|
|
|
if (ee->magic != LAN95XX_EEPROM_MAGIC) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
|
|
|
|
ee->magic);
|
2008-10-02 13:27:57 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
|
|
|
|
}
|
|
|
|
|
2012-07-10 05:44:45 +08:00
|
|
|
static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
|
|
|
|
{
|
|
|
|
/* all smsc95xx registers */
|
|
|
|
return COE_CR - ID_REV + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
|
|
|
|
void *buf)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
2012-07-11 04:32:51 +08:00
|
|
|
unsigned int i, j;
|
|
|
|
int retval;
|
2012-07-10 05:44:45 +08:00
|
|
|
u32 *data = buf;
|
|
|
|
|
|
|
|
retval = smsc95xx_read_reg(dev, ID_REV, ®s->version);
|
|
|
|
if (retval < 0) {
|
|
|
|
netdev_warn(netdev, "REGS: cannot read ID_REV\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
|
|
|
|
retval = smsc95xx_read_reg(dev, i, &data[j]);
|
|
|
|
if (retval < 0) {
|
|
|
|
netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
static void smsc95xx_ethtool_get_wol(struct net_device *net,
|
|
|
|
struct ethtool_wolinfo *wolinfo)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(net);
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
|
|
|
|
wolinfo->supported = SUPPORTED_WAKE;
|
|
|
|
wolinfo->wolopts = pdata->wolopts;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_ethtool_set_wol(struct net_device *net,
|
|
|
|
struct ethtool_wolinfo *wolinfo)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(net);
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
|
|
|
|
pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-09-02 16:03:33 +08:00
|
|
|
static const struct ethtool_ops smsc95xx_ethtool_ops = {
|
2008-10-02 13:27:57 +08:00
|
|
|
.get_link = usbnet_get_link,
|
|
|
|
.nway_reset = usbnet_nway_reset,
|
|
|
|
.get_drvinfo = usbnet_get_drvinfo,
|
|
|
|
.get_msglevel = usbnet_get_msglevel,
|
|
|
|
.set_msglevel = usbnet_set_msglevel,
|
|
|
|
.get_settings = usbnet_get_settings,
|
|
|
|
.set_settings = usbnet_set_settings,
|
|
|
|
.get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
|
|
|
|
.get_eeprom = smsc95xx_ethtool_get_eeprom,
|
|
|
|
.set_eeprom = smsc95xx_ethtool_set_eeprom,
|
2012-07-10 05:44:45 +08:00
|
|
|
.get_regs_len = smsc95xx_ethtool_getregslen,
|
|
|
|
.get_regs = smsc95xx_ethtool_getregs,
|
2012-09-28 08:07:12 +08:00
|
|
|
.get_wol = smsc95xx_ethtool_get_wol,
|
|
|
|
.set_wol = smsc95xx_ethtool_set_wol,
|
2008-10-02 13:27:57 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = netdev_priv(netdev);
|
|
|
|
|
|
|
|
if (!netif_running(netdev))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smsc95xx_init_mac_address(struct usbnet *dev)
|
|
|
|
{
|
|
|
|
/* try reading mac address from EEPROM */
|
|
|
|
if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
|
|
|
|
dev->net->dev_addr) == 0) {
|
|
|
|
if (is_valid_ether_addr(dev->net->dev_addr)) {
|
|
|
|
/* eeprom values are valid so use them */
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* no eeprom, or eeprom values are invalid. generate random MAC */
|
2012-02-15 14:45:39 +08:00
|
|
|
eth_hw_addr_random(dev->net);
|
2012-07-13 03:33:07 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_set_mac_address(struct usbnet *dev)
|
|
|
|
{
|
|
|
|
u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
|
|
|
|
dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
|
|
|
|
u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write ADDRL: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write ADDRH: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* starts the TX path */
|
2012-09-28 08:07:09 +08:00
|
|
|
static int smsc95xx_start_tx_path(struct usbnet *dev)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
unsigned long flags;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* Enable Tx at MAC */
|
|
|
|
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
|
|
|
|
pdata->mac_cr |= MAC_CR_TXEN_;
|
|
|
|
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
|
|
|
|
check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* Enable Tx at SCSRs */
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
|
|
|
|
check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret);
|
|
|
|
|
|
|
|
return 0;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Starts the Receive path */
|
2012-11-06 12:53:07 +08:00
|
|
|
static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
|
2008-10-02 13:27:57 +08:00
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
unsigned long flags;
|
2012-09-28 08:07:09 +08:00
|
|
|
int ret;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
|
|
|
|
pdata->mac_cr |= MAC_CR_RXEN_;
|
|
|
|
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
|
|
|
|
|
|
|
|
return 0;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_phy_initialize(struct usbnet *dev)
|
|
|
|
{
|
2012-09-28 08:07:09 +08:00
|
|
|
int bmcr, ret, timeout = 0;
|
2010-03-16 17:03:06 +08:00
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
/* Initialize MII structure */
|
|
|
|
dev->mii.dev = dev->net;
|
|
|
|
dev->mii.mdio_read = smsc95xx_mdio_read;
|
|
|
|
dev->mii.mdio_write = smsc95xx_mdio_write;
|
|
|
|
dev->mii.phy_id_mask = 0x1f;
|
|
|
|
dev->mii.reg_num_mask = 0x1f;
|
|
|
|
dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
|
|
|
|
|
2010-03-16 17:03:06 +08:00
|
|
|
/* reset phy and wait for reset to complete */
|
2008-10-02 13:27:57 +08:00
|
|
|
smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
|
2010-03-16 17:03:06 +08:00
|
|
|
|
|
|
|
do {
|
|
|
|
msleep(10);
|
|
|
|
bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
|
|
|
|
timeout++;
|
2011-04-30 16:29:27 +08:00
|
|
|
} while ((bmcr & BMCR_RESET) && (timeout < 100));
|
2010-03-16 17:03:06 +08:00
|
|
|
|
|
|
|
if (timeout >= 100) {
|
|
|
|
netdev_warn(dev->net, "timeout on PHY Reset");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
|
|
|
|
ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
|
|
|
|
ADVERTISE_PAUSE_ASYM);
|
|
|
|
|
|
|
|
/* read to clear */
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
|
|
|
|
check_warn_return(ret, "Failed to read PHY_INT_SRC during init");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
|
|
|
|
PHY_INT_MASK_DEFAULT_);
|
|
|
|
mii_nway_restart(&dev->mii);
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_reset(struct usbnet *dev)
|
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
u32 read_buf, write_buf, burst_cap;
|
|
|
|
int ret = 0, timeout;
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
2012-09-28 08:07:07 +08:00
|
|
|
msleep(10);
|
2008-10-02 13:27:57 +08:00
|
|
|
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
timeout++;
|
|
|
|
} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
|
|
|
|
|
|
|
|
if (timeout >= 100) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
timeout = 0;
|
|
|
|
do {
|
2012-09-28 08:07:07 +08:00
|
|
|
msleep(10);
|
2008-10-02 13:27:57 +08:00
|
|
|
ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
timeout++;
|
|
|
|
} while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
|
|
|
|
|
|
|
|
if (timeout >= 100) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = smsc95xx_set_mac_address(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"MAC Address: %pM\n", dev->net->dev_addr);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from HW_CFG : 0x%08x\n", read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
read_buf |= HW_CFG_BIR_;
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
|
|
|
|
read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (!turbo_mode) {
|
|
|
|
burst_cap = 0;
|
|
|
|
dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
|
|
|
|
} else if (dev->udev->speed == USB_SPEED_HIGH) {
|
|
|
|
burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
|
|
|
|
dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
|
|
|
|
} else {
|
|
|
|
burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
|
|
|
|
dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
|
|
|
|
}
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from BURST_CAP after writing: 0x%08x\n",
|
|
|
|
read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from BULK_IN_DLY after writing: 0x%08x\n",
|
|
|
|
read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from HW_CFG: 0x%08x\n", read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (turbo_mode)
|
|
|
|
read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
|
|
|
|
|
|
|
|
read_buf &= ~HW_CFG_RXDOFF_;
|
|
|
|
|
|
|
|
/* set Rx data offset=2, Make IP header aligns on word boundary. */
|
|
|
|
read_buf |= NET_IP_ALIGN << 9;
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
|
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net,
|
|
|
|
"Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2009-05-01 13:46:51 +08:00
|
|
|
/* Configure GPIO pins as LED outputs */
|
|
|
|
write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
|
|
|
|
LED_GPIO_CFG_FDX_LED;
|
|
|
|
ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret);
|
2009-05-01 13:46:51 +08:00
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
/* Init Tx */
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, FLOW, 0);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* Don't need mac_cr_lock during initialisation */
|
|
|
|
ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* Init Rx */
|
|
|
|
/* Set Vlan */
|
2012-09-28 08:07:08 +08:00
|
|
|
ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write VLAN1: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2008-11-20 20:19:21 +08:00
|
|
|
/* Enable or disable checksum offload engines */
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_set_features(dev->net, dev->net->features);
|
|
|
|
check_warn_return(ret, "Failed to set checksum offload features");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
smsc95xx_set_multicast(dev->net);
|
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_phy_initialize(dev);
|
|
|
|
check_warn_return(ret, "Failed to init PHY");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
/* enable PHY interrupts */
|
|
|
|
read_buf |= INT_EP_CTL_PHY_INT_;
|
|
|
|
|
|
|
|
ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2012-09-28 08:07:09 +08:00
|
|
|
ret = smsc95xx_start_tx_path(dev);
|
|
|
|
check_warn_return(ret, "Failed to start TX path");
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_start_rx_path(dev, 0);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "Failed to start RX path");
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-03-21 03:35:58 +08:00
|
|
|
static const struct net_device_ops smsc95xx_netdev_ops = {
|
|
|
|
.ndo_open = usbnet_open,
|
|
|
|
.ndo_stop = usbnet_stop,
|
|
|
|
.ndo_start_xmit = usbnet_start_xmit,
|
|
|
|
.ndo_tx_timeout = usbnet_tx_timeout,
|
|
|
|
.ndo_change_mtu = usbnet_change_mtu,
|
|
|
|
.ndo_set_mac_address = eth_mac_addr,
|
|
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
|
|
.ndo_do_ioctl = smsc95xx_ioctl,
|
2011-08-16 14:29:01 +08:00
|
|
|
.ndo_set_rx_mode = smsc95xx_set_multicast,
|
2011-04-02 11:56:23 +08:00
|
|
|
.ndo_set_features = smsc95xx_set_features,
|
2009-03-21 03:35:58 +08:00
|
|
|
};
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
|
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = NULL;
|
2012-10-26 11:43:56 +08:00
|
|
|
u32 val;
|
2008-10-02 13:27:57 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
|
|
|
|
|
|
|
|
ret = usbnet_get_endpoints(dev, intf);
|
2012-09-28 08:07:09 +08:00
|
|
|
check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
if (!pdata) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_init(&pdata->mac_cr_lock);
|
|
|
|
|
2011-04-02 11:56:23 +08:00
|
|
|
if (DEFAULT_TX_CSUM_ENABLE)
|
|
|
|
dev->net->features |= NETIF_F_HW_CSUM;
|
|
|
|
if (DEFAULT_RX_CSUM_ENABLE)
|
|
|
|
dev->net->features |= NETIF_F_RXCSUM;
|
|
|
|
|
|
|
|
dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
2010-10-18 21:16:39 +08:00
|
|
|
smsc95xx_init_mac_address(dev);
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
/* Init all registers */
|
|
|
|
ret = smsc95xx_reset(dev);
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
/* detect device revision as different features may be available */
|
|
|
|
ret = smsc95xx_read_reg(dev, ID_REV, &val);
|
|
|
|
check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
|
|
|
|
val >>= 16;
|
|
|
|
if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9512_))
|
|
|
|
pdata->wuff_filter_count = LAN9500A_WUFF_NUM;
|
|
|
|
else
|
|
|
|
pdata->wuff_filter_count = LAN9500_WUFF_NUM;
|
|
|
|
|
2009-03-21 03:35:58 +08:00
|
|
|
dev->net->netdev_ops = &smsc95xx_netdev_ops;
|
2008-10-02 13:27:57 +08:00
|
|
|
dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
|
|
|
|
dev->net->flags |= IFF_MULTICAST;
|
2011-04-02 11:56:23 +08:00
|
|
|
dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
|
2012-04-20 17:39:23 +08:00
|
|
|
dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
|
|
|
|
{
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
if (pdata) {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, ifdown, dev->net, "free pdata\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
kfree(pdata);
|
|
|
|
pdata = NULL;
|
|
|
|
dev->data[0] = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
static u16 smsc_crc(const u8 *buffer, size_t len, int filter)
|
|
|
|
{
|
|
|
|
return bitrev16(crc16(0xFFFF, buffer, len)) << ((filter % 2) * 16);
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:11 +08:00
|
|
|
static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = usb_get_intfdata(intf);
|
2012-09-28 08:07:12 +08:00
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
2012-09-28 08:07:11 +08:00
|
|
|
int ret;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
ret = usbnet_suspend(intf, message);
|
|
|
|
check_warn_return(ret, "usbnet_suspend error");
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
/* if no wol options set, enter lowest power SUSPEND2 mode */
|
|
|
|
if (!(pdata->wolopts & SUPPORTED_WAKE)) {
|
|
|
|
netdev_info(dev->net, "entering SUSPEND2 mode");
|
|
|
|
|
|
|
|
/* disable energy detect (link up) & wake up events */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading WUCSR");
|
|
|
|
|
|
|
|
val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing WUCSR");
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
|
|
|
val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
|
|
|
|
/* enter suspend2 mode */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
|
|
|
val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
|
|
|
|
val |= PM_CTL_SUS_MODE_2;
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
|
|
|
|
u32 *filter_mask = kzalloc(32, GFP_KERNEL);
|
2012-11-06 12:53:06 +08:00
|
|
|
u32 command[2];
|
|
|
|
u32 offset[2];
|
|
|
|
u32 crc[4];
|
2012-10-26 11:43:56 +08:00
|
|
|
int i, filter = 0;
|
|
|
|
|
2012-11-06 12:53:06 +08:00
|
|
|
memset(command, 0, sizeof(command));
|
|
|
|
memset(offset, 0, sizeof(offset));
|
|
|
|
memset(crc, 0, sizeof(crc));
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
if (pdata->wolopts & WAKE_BCAST) {
|
|
|
|
const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
|
|
|
|
netdev_info(dev->net, "enabling broadcast detection");
|
|
|
|
filter_mask[filter * 4] = 0x003F;
|
|
|
|
filter_mask[filter * 4 + 1] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 2] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 3] = 0x00;
|
|
|
|
command[filter/4] |= 0x05UL << ((filter % 4) * 8);
|
|
|
|
offset[filter/4] |= 0x00 << ((filter % 4) * 8);
|
|
|
|
crc[filter/2] |= smsc_crc(bcast, 6, filter);
|
|
|
|
filter++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->wolopts & WAKE_MCAST) {
|
|
|
|
const u8 mcast[] = {0x01, 0x00, 0x5E};
|
|
|
|
netdev_info(dev->net, "enabling multicast detection");
|
|
|
|
filter_mask[filter * 4] = 0x0007;
|
|
|
|
filter_mask[filter * 4 + 1] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 2] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 3] = 0x00;
|
|
|
|
command[filter/4] |= 0x09UL << ((filter % 4) * 8);
|
|
|
|
offset[filter/4] |= 0x00 << ((filter % 4) * 8);
|
|
|
|
crc[filter/2] |= smsc_crc(mcast, 3, filter);
|
|
|
|
filter++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->wolopts & WAKE_ARP) {
|
|
|
|
const u8 arp[] = {0x08, 0x06};
|
|
|
|
netdev_info(dev->net, "enabling ARP detection");
|
|
|
|
filter_mask[filter * 4] = 0x0003;
|
|
|
|
filter_mask[filter * 4 + 1] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 2] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 3] = 0x00;
|
|
|
|
command[filter/4] |= 0x05UL << ((filter % 4) * 8);
|
|
|
|
offset[filter/4] |= 0x0C << ((filter % 4) * 8);
|
|
|
|
crc[filter/2] |= smsc_crc(arp, 2, filter);
|
|
|
|
filter++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->wolopts & WAKE_UCAST) {
|
|
|
|
netdev_info(dev->net, "enabling unicast detection");
|
|
|
|
filter_mask[filter * 4] = 0x003F;
|
|
|
|
filter_mask[filter * 4 + 1] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 2] = 0x00;
|
|
|
|
filter_mask[filter * 4 + 3] = 0x00;
|
|
|
|
command[filter/4] |= 0x01UL << ((filter % 4) * 8);
|
|
|
|
offset[filter/4] |= 0x00 << ((filter % 4) * 8);
|
|
|
|
crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
|
|
|
|
filter++;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < (pdata->wuff_filter_count * 4); i++) {
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
|
2012-11-06 12:53:06 +08:00
|
|
|
if (ret < 0)
|
|
|
|
kfree(filter_mask);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error writing WUFF");
|
|
|
|
}
|
2012-11-06 12:53:06 +08:00
|
|
|
kfree(filter_mask);
|
2012-10-26 11:43:56 +08:00
|
|
|
|
|
|
|
for (i = 0; i < (pdata->wuff_filter_count / 4); i++) {
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error writing WUFF");
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < (pdata->wuff_filter_count / 4); i++) {
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error writing WUFF");
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < (pdata->wuff_filter_count / 2); i++) {
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error writing WUFF");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear any pending pattern match packet status */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error reading WUCSR");
|
|
|
|
|
|
|
|
val |= WUCSR_WUFR_;
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
|
2012-10-26 11:43:56 +08:00
|
|
|
check_warn_return(ret, "Error writing WUCSR");
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
if (pdata->wolopts & WAKE_MAGIC) {
|
|
|
|
/* clear any pending magic packet status */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading WUCSR");
|
|
|
|
|
|
|
|
val |= WUCSR_MPR_;
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing WUCSR");
|
|
|
|
}
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
/* enable/disable wakeup sources */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading WUCSR");
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
|
|
|
|
netdev_info(dev->net, "enabling pattern match wakeup");
|
|
|
|
val |= WUCSR_WAKE_EN_;
|
|
|
|
} else {
|
|
|
|
netdev_info(dev->net, "disabling pattern match wakeup");
|
|
|
|
val &= ~WUCSR_WAKE_EN_;
|
|
|
|
}
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
if (pdata->wolopts & WAKE_MAGIC) {
|
|
|
|
netdev_info(dev->net, "enabling magic packet wakeup");
|
|
|
|
val |= WUCSR_MPEN_;
|
|
|
|
} else {
|
|
|
|
netdev_info(dev->net, "disabling magic packet wakeup");
|
|
|
|
val &= ~WUCSR_MPEN_;
|
|
|
|
}
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing WUCSR");
|
|
|
|
|
|
|
|
/* enable wol wakeup source */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
|
|
|
val |= PM_CTL_WOL_EN_;
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
/* enable receiver to enable frame reception */
|
2012-11-06 12:53:07 +08:00
|
|
|
smsc95xx_start_rx_path(dev, 1);
|
2012-09-28 08:07:12 +08:00
|
|
|
|
|
|
|
/* some wol options are enabled, so enter SUSPEND0 */
|
|
|
|
netdev_info(dev->net, "entering SUSPEND0 mode");
|
2012-09-28 08:07:11 +08:00
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:11 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
|
|
|
|
val |= PM_CTL_SUS_MODE_0;
|
2012-09-28 08:07:11 +08:00
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:11 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
|
2012-09-28 08:07:12 +08:00
|
|
|
/* clear wol status */
|
|
|
|
val &= ~PM_CTL_WUPS_;
|
|
|
|
val |= PM_CTL_WUPS_WOL_;
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
|
|
|
|
/* read back PM_CTRL */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
|
|
|
smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_resume(struct usb_interface *intf)
|
|
|
|
{
|
|
|
|
struct usbnet *dev = usb_get_intfdata(intf);
|
|
|
|
struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
|
|
|
|
int ret;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
BUG_ON(!dev);
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
if (pdata->wolopts) {
|
2012-09-28 08:07:12 +08:00
|
|
|
smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
/* clear wake-up sources */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading WUCSR");
|
|
|
|
|
2012-10-26 11:43:56 +08:00
|
|
|
val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
|
2012-09-28 08:07:12 +08:00
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing WUCSR");
|
|
|
|
|
|
|
|
/* clear wake-up status */
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error reading PM_CTRL");
|
|
|
|
|
|
|
|
val &= ~PM_CTL_WOL_EN_;
|
|
|
|
val |= PM_CTL_WUPS_;
|
|
|
|
|
2012-11-06 12:53:07 +08:00
|
|
|
ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "Error writing PM_CTRL");
|
|
|
|
}
|
|
|
|
|
2012-11-22 16:05:22 +08:00
|
|
|
ret = usbnet_resume(intf);
|
2012-09-28 08:07:12 +08:00
|
|
|
check_warn_return(ret, "usbnet_resume error");
|
|
|
|
|
2012-09-28 08:07:11 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
|
|
|
|
skb->ip_summed = CHECKSUM_COMPLETE;
|
|
|
|
skb_trim(skb, skb->len - 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
while (skb->len > 0) {
|
|
|
|
u32 header, align_count;
|
|
|
|
struct sk_buff *ax_skb;
|
|
|
|
unsigned char *packet;
|
|
|
|
u16 size;
|
|
|
|
|
|
|
|
memcpy(&header, skb->data, sizeof(header));
|
|
|
|
le32_to_cpus(&header);
|
|
|
|
skb_pull(skb, 4 + NET_IP_ALIGN);
|
|
|
|
packet = skb->data;
|
|
|
|
|
|
|
|
/* get the packet length */
|
|
|
|
size = (u16)((header & RX_STS_FL_) >> 16);
|
|
|
|
align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
|
|
|
|
|
|
|
|
if (unlikely(header & RX_STS_ES_)) {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, rx_err, dev->net,
|
|
|
|
"Error header=0x%08x\n", header);
|
2009-06-30 00:53:00 +08:00
|
|
|
dev->net->stats.rx_errors++;
|
|
|
|
dev->net->stats.rx_dropped++;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if (header & RX_STS_CRC_) {
|
2009-06-30 00:53:00 +08:00
|
|
|
dev->net->stats.rx_crc_errors++;
|
2008-10-02 13:27:57 +08:00
|
|
|
} else {
|
|
|
|
if (header & (RX_STS_TL_ | RX_STS_RF_))
|
2009-06-30 00:53:00 +08:00
|
|
|
dev->net->stats.rx_frame_errors++;
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
if ((header & RX_STS_LE_) &&
|
|
|
|
(!(header & RX_STS_FT_)))
|
2009-06-30 00:53:00 +08:00
|
|
|
dev->net->stats.rx_length_errors++;
|
2008-10-02 13:27:57 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
|
|
|
|
if (unlikely(size > (ETH_FRAME_LEN + 12))) {
|
2010-02-17 18:30:24 +08:00
|
|
|
netif_dbg(dev, rx_err, dev->net,
|
|
|
|
"size err header=0x%08x\n", header);
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* last frame in this batch */
|
|
|
|
if (skb->len == size) {
|
2011-04-02 11:56:23 +08:00
|
|
|
if (dev->net->features & NETIF_F_RXCSUM)
|
2008-10-02 13:27:57 +08:00
|
|
|
smsc95xx_rx_csum_offload(skb);
|
2009-05-13 18:10:41 +08:00
|
|
|
skb_trim(skb, skb->len - 4); /* remove fcs */
|
2008-10-02 13:27:57 +08:00
|
|
|
skb->truesize = size + sizeof(struct sk_buff);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ax_skb = skb_clone(skb, GFP_ATOMIC);
|
|
|
|
if (unlikely(!ax_skb)) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "Error allocating skb\n");
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ax_skb->len = size;
|
|
|
|
ax_skb->data = packet;
|
|
|
|
skb_set_tail_pointer(ax_skb, size);
|
|
|
|
|
2011-04-02 11:56:23 +08:00
|
|
|
if (dev->net->features & NETIF_F_RXCSUM)
|
2008-10-02 13:27:57 +08:00
|
|
|
smsc95xx_rx_csum_offload(ax_skb);
|
2009-05-13 18:10:41 +08:00
|
|
|
skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
|
2008-10-02 13:27:57 +08:00
|
|
|
ax_skb->truesize = size + sizeof(struct sk_buff);
|
|
|
|
|
|
|
|
usbnet_skb_return(dev, ax_skb);
|
|
|
|
}
|
|
|
|
|
|
|
|
skb_pull(skb, size);
|
|
|
|
|
|
|
|
/* padding bytes before the next frame starts */
|
|
|
|
if (skb->len)
|
|
|
|
skb_pull(skb, align_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(skb->len < 0)) {
|
2010-02-17 18:30:23 +08:00
|
|
|
netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
|
2008-10-02 13:27:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2008-11-20 20:19:21 +08:00
|
|
|
static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
|
|
|
|
{
|
2010-12-14 23:24:08 +08:00
|
|
|
u16 low_16 = (u16)skb_checksum_start_offset(skb);
|
|
|
|
u16 high_16 = low_16 + skb->csum_offset;
|
2008-11-20 20:19:21 +08:00
|
|
|
return (high_16 << 16) | low_16;
|
|
|
|
}
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
|
|
|
|
struct sk_buff *skb, gfp_t flags)
|
|
|
|
{
|
2011-04-02 11:56:23 +08:00
|
|
|
bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
|
2008-11-20 20:19:21 +08:00
|
|
|
int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
|
2008-10-02 13:27:57 +08:00
|
|
|
u32 tx_cmd_a, tx_cmd_b;
|
|
|
|
|
2008-11-20 20:19:21 +08:00
|
|
|
/* We do not advertise SG, so skbs should be already linearized */
|
|
|
|
BUG_ON(skb_shinfo(skb)->nr_frags);
|
|
|
|
|
|
|
|
if (skb_headroom(skb) < overhead) {
|
2008-10-02 13:27:57 +08:00
|
|
|
struct sk_buff *skb2 = skb_copy_expand(skb,
|
2008-11-20 20:19:21 +08:00
|
|
|
overhead, 0, flags);
|
2008-10-02 13:27:57 +08:00
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
skb = skb2;
|
|
|
|
if (!skb)
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2008-11-20 20:19:21 +08:00
|
|
|
if (csum) {
|
2010-03-19 13:18:41 +08:00
|
|
|
if (skb->len <= 45) {
|
|
|
|
/* workaround - hardware tx checksum does not work
|
|
|
|
* properly with extremely small packets */
|
2010-12-14 23:24:08 +08:00
|
|
|
long csstart = skb_checksum_start_offset(skb);
|
2010-03-19 13:18:41 +08:00
|
|
|
__wsum calc = csum_partial(skb->data + csstart,
|
|
|
|
skb->len - csstart, 0);
|
|
|
|
*((__sum16 *)(skb->data + csstart
|
|
|
|
+ skb->csum_offset)) = csum_fold(calc);
|
|
|
|
|
|
|
|
csum = false;
|
|
|
|
} else {
|
|
|
|
u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
|
|
|
|
skb_push(skb, 4);
|
2012-11-02 08:44:20 +08:00
|
|
|
cpu_to_le32s(&csum_preamble);
|
2010-03-19 13:18:41 +08:00
|
|
|
memcpy(skb->data, &csum_preamble, 4);
|
|
|
|
}
|
2008-11-20 20:19:21 +08:00
|
|
|
}
|
|
|
|
|
2008-10-02 13:27:57 +08:00
|
|
|
skb_push(skb, 4);
|
|
|
|
tx_cmd_b = (u32)(skb->len - 4);
|
2008-11-20 20:19:21 +08:00
|
|
|
if (csum)
|
|
|
|
tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
|
2008-10-02 13:27:57 +08:00
|
|
|
cpu_to_le32s(&tx_cmd_b);
|
|
|
|
memcpy(skb->data, &tx_cmd_b, 4);
|
|
|
|
|
|
|
|
skb_push(skb, 4);
|
|
|
|
tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
|
|
|
|
TX_CMD_A_LAST_SEG_;
|
|
|
|
cpu_to_le32s(&tx_cmd_a);
|
|
|
|
memcpy(skb->data, &tx_cmd_a, 4);
|
|
|
|
|
|
|
|
return skb;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct driver_info smsc95xx_info = {
|
|
|
|
.description = "smsc95xx USB 2.0 Ethernet",
|
|
|
|
.bind = smsc95xx_bind,
|
|
|
|
.unbind = smsc95xx_unbind,
|
|
|
|
.link_reset = smsc95xx_link_reset,
|
|
|
|
.reset = smsc95xx_reset,
|
|
|
|
.rx_fixup = smsc95xx_rx_fixup,
|
|
|
|
.tx_fixup = smsc95xx_tx_fixup,
|
|
|
|
.status = smsc95xx_status,
|
2012-04-23 12:05:20 +08:00
|
|
|
.flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
|
2008-10-02 13:27:57 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct usb_device_id products[] = {
|
|
|
|
{
|
|
|
|
/* SMSC9500 USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9500),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
2009-09-22 13:13:02 +08:00
|
|
|
{
|
|
|
|
/* SMSC9505 USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9505),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9500A USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9E00),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9505A USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9E01),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
2009-05-01 14:07:22 +08:00
|
|
|
{
|
|
|
|
/* SMSC9512/9514 USB Hub & Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0xec00),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
2009-09-22 13:13:02 +08:00
|
|
|
{
|
|
|
|
/* SMSC9500 USB Ethernet Device (SAL10) */
|
|
|
|
USB_DEVICE(0x0424, 0x9900),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9505 USB Ethernet Device (SAL10) */
|
|
|
|
USB_DEVICE(0x0424, 0x9901),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9500A USB Ethernet Device (SAL10) */
|
|
|
|
USB_DEVICE(0x0424, 0x9902),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9505A USB Ethernet Device (SAL10) */
|
|
|
|
USB_DEVICE(0x0424, 0x9903),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
|
|
|
|
USB_DEVICE(0x0424, 0x9904),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9500A USB Ethernet Device (HAL) */
|
|
|
|
USB_DEVICE(0x0424, 0x9905),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9505A USB Ethernet Device (HAL) */
|
|
|
|
USB_DEVICE(0x0424, 0x9906),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9500 USB Ethernet Device (Alternate ID) */
|
|
|
|
USB_DEVICE(0x0424, 0x9907),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9500A USB Ethernet Device (Alternate ID) */
|
|
|
|
USB_DEVICE(0x0424, 0x9908),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
|
|
|
|
USB_DEVICE(0x0424, 0x9909),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
2011-04-11 09:59:27 +08:00
|
|
|
{
|
|
|
|
/* SMSC LAN9530 USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9530),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC LAN9730 USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9730),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* SMSC LAN89530 USB Ethernet Device */
|
|
|
|
USB_DEVICE(0x0424, 0x9E08),
|
|
|
|
.driver_info = (unsigned long) &smsc95xx_info,
|
|
|
|
},
|
2008-10-02 13:27:57 +08:00
|
|
|
{ }, /* END */
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(usb, products);
|
|
|
|
|
|
|
|
static struct usb_driver smsc95xx_driver = {
|
|
|
|
.name = "smsc95xx",
|
|
|
|
.id_table = products,
|
|
|
|
.probe = usbnet_probe,
|
2012-09-28 08:07:11 +08:00
|
|
|
.suspend = smsc95xx_suspend,
|
2012-09-28 08:07:12 +08:00
|
|
|
.resume = smsc95xx_resume,
|
|
|
|
.reset_resume = smsc95xx_resume,
|
2008-10-02 13:27:57 +08:00
|
|
|
.disconnect = usbnet_disconnect,
|
2012-04-24 01:08:51 +08:00
|
|
|
.disable_hub_initiated_lpm = 1,
|
2008-10-02 13:27:57 +08:00
|
|
|
};
|
|
|
|
|
2011-11-19 01:44:20 +08:00
|
|
|
module_usb_driver(smsc95xx_driver);
|
2008-10-02 13:27:57 +08:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Nancy Lin");
|
2012-04-16 19:13:29 +08:00
|
|
|
MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
|
2008-10-02 13:27:57 +08:00
|
|
|
MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
|
|
|
|
MODULE_LICENSE("GPL");
|