2018-01-22 17:27:00 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2019-04-18 21:38:53 +08:00
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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2018-01-22 17:27:00 +08:00
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2018-01-22 17:27:03 +08:00
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#include <crypto/internal/aead.h>
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2018-01-22 17:27:00 +08:00
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#include <crypto/authenc.h>
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#include <crypto/scatterwalk.h>
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#include <linux/dmapool.h>
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#include <linux/dma-mapping.h>
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#include "cc_buffer_mgr.h"
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#include "cc_lli_defs.h"
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2018-01-22 17:27:01 +08:00
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#include "cc_cipher.h"
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2018-01-22 17:27:02 +08:00
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#include "cc_hash.h"
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2018-01-22 17:27:03 +08:00
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#include "cc_aead.h"
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2018-01-22 17:27:00 +08:00
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union buffer_array_entry {
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struct scatterlist *sgl;
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dma_addr_t buffer_dma;
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};
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struct buffer_array {
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unsigned int num_of_buffers;
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union buffer_array_entry entry[MAX_NUM_OF_BUFFERS_IN_MLLI];
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unsigned int offset[MAX_NUM_OF_BUFFERS_IN_MLLI];
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int nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
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int total_data_len[MAX_NUM_OF_BUFFERS_IN_MLLI];
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bool is_last[MAX_NUM_OF_BUFFERS_IN_MLLI];
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u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
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};
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static inline char *cc_dma_buf_type(enum cc_req_dma_buf_type type)
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{
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switch (type) {
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case CC_DMA_BUF_NULL:
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return "BUF_NULL";
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case CC_DMA_BUF_DLLI:
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return "BUF_DLLI";
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case CC_DMA_BUF_MLLI:
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return "BUF_MLLI";
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default:
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return "BUF_INVALID";
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}
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}
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2018-01-22 17:27:03 +08:00
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/**
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* cc_copy_mac() - Copy MAC to temporary location
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*
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* @dev: device object
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* @req: aead request object
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* @dir: [IN] copy from/to sgl
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*/
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static void cc_copy_mac(struct device *dev, struct aead_request *req,
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enum cc_sg_cpy_direct dir)
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{
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struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
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2020-03-08 23:57:09 +08:00
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u32 skip = req->assoclen + req->cryptlen;
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2018-01-22 17:27:03 +08:00
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cc_copy_sg_portion(dev, areq_ctx->backup_mac, req->src,
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(skip - areq_ctx->req_authsize), skip, dir);
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}
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2018-01-22 17:27:00 +08:00
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/**
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* cc_get_sgl_nents() - Get scatterlist number of entries.
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*
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2020-02-12 02:19:19 +08:00
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* @dev: Device object
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2018-01-22 17:27:00 +08:00
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* @sg_list: SG list
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* @nbytes: [IN] Total SGL data bytes.
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* @lbytes: [OUT] Returns the amount of bytes at the last entry
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2020-02-12 02:19:19 +08:00
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*
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* Return:
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* Number of entries in the scatterlist
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2018-01-22 17:27:00 +08:00
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*/
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static unsigned int cc_get_sgl_nents(struct device *dev,
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struct scatterlist *sg_list,
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2019-04-18 21:38:48 +08:00
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unsigned int nbytes, u32 *lbytes)
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2018-01-22 17:27:00 +08:00
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{
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unsigned int nents = 0;
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2020-01-29 22:37:54 +08:00
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*lbytes = 0;
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2018-01-22 17:27:00 +08:00
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while (nbytes && sg_list) {
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2019-04-18 21:38:48 +08:00
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nents++;
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/* get the number of bytes in the last entry */
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*lbytes = nbytes;
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nbytes -= (sg_list->length > nbytes) ?
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nbytes : sg_list->length;
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sg_list = sg_next(sg_list);
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2018-01-22 17:27:00 +08:00
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}
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2020-01-29 22:37:54 +08:00
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2018-01-22 17:27:00 +08:00
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dev_dbg(dev, "nents %d last bytes %d\n", nents, *lbytes);
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return nents;
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}
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/**
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* cc_copy_sg_portion() - Copy scatter list data,
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* from to_skip to end, to dest and vice versa
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*
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2020-02-12 02:19:19 +08:00
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* @dev: Device object
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* @dest: Buffer to copy to/from
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* @sg: SG list
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* @to_skip: Number of bytes to skip before copying
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* @end: Offset of last byte to copy
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* @direct: Transfer direction (true == from SG list to buffer, false == from
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* buffer to SG list)
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2018-01-22 17:27:00 +08:00
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*/
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void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg,
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u32 to_skip, u32 end, enum cc_sg_cpy_direct direct)
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{
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2019-04-18 21:38:52 +08:00
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u32 nents;
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2018-01-22 17:27:00 +08:00
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2019-04-18 21:38:52 +08:00
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nents = sg_nents_for_len(sg, end);
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2020-02-12 02:18:58 +08:00
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sg_copy_buffer(sg, nents, dest, (end - to_skip + 1), to_skip,
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2018-01-22 17:27:00 +08:00
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(direct == CC_SG_TO_BUF));
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}
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static int cc_render_buff_to_mlli(struct device *dev, dma_addr_t buff_dma,
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u32 buff_size, u32 *curr_nents,
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u32 **mlli_entry_pp)
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{
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u32 *mlli_entry_p = *mlli_entry_pp;
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u32 new_nents;
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/* Verify there is no memory overflow*/
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new_nents = (*curr_nents + buff_size / CC_MAX_MLLI_ENTRY_SIZE + 1);
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2019-01-15 21:43:12 +08:00
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if (new_nents > MAX_NUM_OF_TOTAL_MLLI_ENTRIES) {
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dev_err(dev, "Too many mlli entries. current %d max %d\n",
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new_nents, MAX_NUM_OF_TOTAL_MLLI_ENTRIES);
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2018-01-22 17:27:00 +08:00
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return -ENOMEM;
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2019-01-15 21:43:12 +08:00
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}
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2018-01-22 17:27:00 +08:00
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/*handle buffer longer than 64 kbytes */
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while (buff_size > CC_MAX_MLLI_ENTRY_SIZE) {
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cc_lli_set_addr(mlli_entry_p, buff_dma);
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cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE);
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dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n",
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*curr_nents, mlli_entry_p[LLI_WORD0_OFFSET],
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mlli_entry_p[LLI_WORD1_OFFSET]);
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buff_dma += CC_MAX_MLLI_ENTRY_SIZE;
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buff_size -= CC_MAX_MLLI_ENTRY_SIZE;
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mlli_entry_p = mlli_entry_p + 2;
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(*curr_nents)++;
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}
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/*Last entry */
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cc_lli_set_addr(mlli_entry_p, buff_dma);
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cc_lli_set_size(mlli_entry_p, buff_size);
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dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n",
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*curr_nents, mlli_entry_p[LLI_WORD0_OFFSET],
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mlli_entry_p[LLI_WORD1_OFFSET]);
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mlli_entry_p = mlli_entry_p + 2;
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*mlli_entry_pp = mlli_entry_p;
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(*curr_nents)++;
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return 0;
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}
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static int cc_render_sg_to_mlli(struct device *dev, struct scatterlist *sgl,
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u32 sgl_data_len, u32 sgl_offset,
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u32 *curr_nents, u32 **mlli_entry_pp)
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{
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struct scatterlist *curr_sgl = sgl;
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u32 *mlli_entry_p = *mlli_entry_pp;
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s32 rc = 0;
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for ( ; (curr_sgl && sgl_data_len);
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curr_sgl = sg_next(curr_sgl)) {
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u32 entry_data_len =
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(sgl_data_len > sg_dma_len(curr_sgl) - sgl_offset) ?
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sg_dma_len(curr_sgl) - sgl_offset :
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sgl_data_len;
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sgl_data_len -= entry_data_len;
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rc = cc_render_buff_to_mlli(dev, sg_dma_address(curr_sgl) +
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sgl_offset, entry_data_len,
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curr_nents, &mlli_entry_p);
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if (rc)
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return rc;
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sgl_offset = 0;
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}
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*mlli_entry_pp = mlli_entry_p;
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return 0;
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}
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static int cc_generate_mlli(struct device *dev, struct buffer_array *sg_data,
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struct mlli_params *mlli_params, gfp_t flags)
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{
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u32 *mlli_p;
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u32 total_nents = 0, prev_total_nents = 0;
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int rc = 0, i;
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dev_dbg(dev, "NUM of SG's = %d\n", sg_data->num_of_buffers);
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/* Allocate memory from the pointed pool */
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mlli_params->mlli_virt_addr =
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dma_pool_alloc(mlli_params->curr_pool, flags,
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&mlli_params->mlli_dma_addr);
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if (!mlli_params->mlli_virt_addr) {
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dev_err(dev, "dma_pool_alloc() failed\n");
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rc = -ENOMEM;
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goto build_mlli_exit;
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}
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/* Point to start of MLLI */
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2020-02-12 02:19:03 +08:00
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mlli_p = mlli_params->mlli_virt_addr;
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2018-01-22 17:27:00 +08:00
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/* go over all SG's and link it to one MLLI table */
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for (i = 0; i < sg_data->num_of_buffers; i++) {
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union buffer_array_entry *entry = &sg_data->entry[i];
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u32 tot_len = sg_data->total_data_len[i];
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u32 offset = sg_data->offset[i];
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2020-03-08 23:57:09 +08:00
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rc = cc_render_sg_to_mlli(dev, entry->sgl, tot_len, offset,
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&total_nents, &mlli_p);
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2018-01-22 17:27:00 +08:00
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if (rc)
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return rc;
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/* set last bit in the current table */
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if (sg_data->mlli_nents[i]) {
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/*Calculate the current MLLI table length for the
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*length field in the descriptor
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*/
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*sg_data->mlli_nents[i] +=
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(total_nents - prev_total_nents);
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prev_total_nents = total_nents;
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}
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}
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/* Set MLLI size for the bypass operation */
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mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE);
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dev_dbg(dev, "MLLI params: virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
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mlli_params->mlli_virt_addr, &mlli_params->mlli_dma_addr,
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mlli_params->mlli_len);
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build_mlli_exit:
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return rc;
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}
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static void cc_add_sg_entry(struct device *dev, struct buffer_array *sgl_data,
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unsigned int nents, struct scatterlist *sgl,
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unsigned int data_len, unsigned int data_offset,
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bool is_last_table, u32 *mlli_nents)
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{
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unsigned int index = sgl_data->num_of_buffers;
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dev_dbg(dev, "index=%u nents=%u sgl=%pK data_len=0x%08X is_last=%d\n",
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index, nents, sgl, data_len, is_last_table);
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sgl_data->nents[index] = nents;
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sgl_data->entry[index].sgl = sgl;
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sgl_data->offset[index] = data_offset;
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sgl_data->total_data_len[index] = data_len;
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sgl_data->is_last[index] = is_last_table;
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sgl_data->mlli_nents[index] = mlli_nents;
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if (sgl_data->mlli_nents[index])
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*sgl_data->mlli_nents[index] = 0;
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sgl_data->num_of_buffers++;
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}
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static int cc_map_sg(struct device *dev, struct scatterlist *sg,
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unsigned int nbytes, int direction, u32 *nents,
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u32 max_sg_nents, u32 *lbytes, u32 *mapped_nents)
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{
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2020-01-29 22:37:54 +08:00
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int ret = 0;
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*nents = cc_get_sgl_nents(dev, sg, nbytes, lbytes);
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if (*nents > max_sg_nents) {
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*nents = 0;
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dev_err(dev, "Too many fragments. current %d max %d\n",
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*nents, max_sg_nents);
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return -ENOMEM;
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2018-01-22 17:27:00 +08:00
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}
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2020-01-29 22:37:54 +08:00
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ret = dma_map_sg(dev, sg, *nents, direction);
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if (dma_mapping_error(dev, ret)) {
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*nents = 0;
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dev_err(dev, "dma_map_sg() sg buffer failed %d\n", ret);
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return -ENOMEM;
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}
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*mapped_nents = ret;
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2018-01-22 17:27:00 +08:00
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return 0;
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}
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2018-01-22 17:27:03 +08:00
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static int
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cc_set_aead_conf_buf(struct device *dev, struct aead_req_ctx *areq_ctx,
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u8 *config_data, struct buffer_array *sg_data,
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unsigned int assoclen)
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{
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dev_dbg(dev, " handle additional data config set to DLLI\n");
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/* create sg for the current buffer */
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sg_init_one(&areq_ctx->ccm_adata_sg, config_data,
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AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size);
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if (dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE) != 1) {
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dev_err(dev, "dma_map_sg() config buffer failed\n");
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return -ENOMEM;
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}
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dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
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&sg_dma_address(&areq_ctx->ccm_adata_sg),
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sg_page(&areq_ctx->ccm_adata_sg),
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sg_virt(&areq_ctx->ccm_adata_sg),
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areq_ctx->ccm_adata_sg.offset, areq_ctx->ccm_adata_sg.length);
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/* prepare for case of MLLI */
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if (assoclen > 0) {
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cc_add_sg_entry(dev, sg_data, 1, &areq_ctx->ccm_adata_sg,
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(AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size),
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0, false, NULL);
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}
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return 0;
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}
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|
|
2018-01-22 17:27:02 +08:00
|
|
|
static int cc_set_hash_buf(struct device *dev, struct ahash_req_ctx *areq_ctx,
|
|
|
|
u8 *curr_buff, u32 curr_buff_cnt,
|
|
|
|
struct buffer_array *sg_data)
|
|
|
|
{
|
|
|
|
dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt);
|
|
|
|
/* create sg for the current buffer */
|
|
|
|
sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
|
|
|
|
if (dma_map_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE) != 1) {
|
|
|
|
dev_err(dev, "dma_map_sg() src buffer failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
|
|
|
|
&sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg),
|
|
|
|
sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset,
|
|
|
|
areq_ctx->buff_sg->length);
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
|
|
|
|
areq_ctx->curr_sg = areq_ctx->buff_sg;
|
|
|
|
areq_ctx->in_nents = 0;
|
|
|
|
/* prepare for case of MLLI */
|
|
|
|
cc_add_sg_entry(dev, sg_data, 1, areq_ctx->buff_sg, curr_buff_cnt, 0,
|
|
|
|
false, NULL);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-22 17:27:01 +08:00
|
|
|
void cc_unmap_cipher_request(struct device *dev, void *ctx,
|
2018-01-22 17:27:02 +08:00
|
|
|
unsigned int ivsize, struct scatterlist *src,
|
|
|
|
struct scatterlist *dst)
|
2018-01-22 17:27:01 +08:00
|
|
|
{
|
|
|
|
struct cipher_req_ctx *req_ctx = (struct cipher_req_ctx *)ctx;
|
|
|
|
|
|
|
|
if (req_ctx->gen_ctx.iv_dma_addr) {
|
|
|
|
dev_dbg(dev, "Unmapped iv: iv_dma_addr=%pad iv_size=%u\n",
|
|
|
|
&req_ctx->gen_ctx.iv_dma_addr, ivsize);
|
|
|
|
dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr,
|
2019-04-18 21:38:44 +08:00
|
|
|
ivsize, DMA_BIDIRECTIONAL);
|
2018-01-22 17:27:01 +08:00
|
|
|
}
|
|
|
|
/* Release pool */
|
|
|
|
if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI &&
|
|
|
|
req_ctx->mlli_params.mlli_virt_addr) {
|
|
|
|
dma_pool_free(req_ctx->mlli_params.curr_pool,
|
|
|
|
req_ctx->mlli_params.mlli_virt_addr,
|
|
|
|
req_ctx->mlli_params.mlli_dma_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL);
|
|
|
|
dev_dbg(dev, "Unmapped req->src=%pK\n", sg_virt(src));
|
|
|
|
|
|
|
|
if (src != dst) {
|
|
|
|
dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL);
|
|
|
|
dev_dbg(dev, "Unmapped req->dst=%pK\n", sg_virt(dst));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int cc_map_cipher_request(struct cc_drvdata *drvdata, void *ctx,
|
|
|
|
unsigned int ivsize, unsigned int nbytes,
|
|
|
|
void *info, struct scatterlist *src,
|
|
|
|
struct scatterlist *dst, gfp_t flags)
|
|
|
|
{
|
|
|
|
struct cipher_req_ctx *req_ctx = (struct cipher_req_ctx *)ctx;
|
|
|
|
struct mlli_params *mlli_params = &req_ctx->mlli_params;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
struct buffer_array sg_data;
|
|
|
|
u32 dummy = 0;
|
|
|
|
int rc = 0;
|
|
|
|
u32 mapped_nents = 0;
|
|
|
|
|
|
|
|
req_ctx->dma_buf_type = CC_DMA_BUF_DLLI;
|
|
|
|
mlli_params->curr_pool = NULL;
|
|
|
|
sg_data.num_of_buffers = 0;
|
|
|
|
|
|
|
|
/* Map IV buffer */
|
|
|
|
if (ivsize) {
|
2020-02-12 02:18:58 +08:00
|
|
|
dump_byte_array("iv", info, ivsize);
|
2018-01-22 17:27:01 +08:00
|
|
|
req_ctx->gen_ctx.iv_dma_addr =
|
2020-02-12 02:18:58 +08:00
|
|
|
dma_map_single(dev, info, ivsize, DMA_BIDIRECTIONAL);
|
2018-01-22 17:27:01 +08:00
|
|
|
if (dma_mapping_error(dev, req_ctx->gen_ctx.iv_dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n",
|
|
|
|
ivsize, info);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n",
|
|
|
|
ivsize, info, &req_ctx->gen_ctx.iv_dma_addr);
|
|
|
|
} else {
|
|
|
|
req_ctx->gen_ctx.iv_dma_addr = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Map the src SGL */
|
|
|
|
rc = cc_map_sg(dev, src, nbytes, DMA_BIDIRECTIONAL, &req_ctx->in_nents,
|
|
|
|
LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents);
|
2019-01-15 21:43:11 +08:00
|
|
|
if (rc)
|
2018-01-22 17:27:01 +08:00
|
|
|
goto cipher_exit;
|
|
|
|
if (mapped_nents > 1)
|
|
|
|
req_ctx->dma_buf_type = CC_DMA_BUF_MLLI;
|
|
|
|
|
|
|
|
if (src == dst) {
|
|
|
|
/* Handle inplace operation */
|
|
|
|
if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
|
|
|
|
req_ctx->out_nents = 0;
|
|
|
|
cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src,
|
|
|
|
nbytes, 0, true,
|
|
|
|
&req_ctx->in_mlli_nents);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Map the dst sg */
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_map_sg(dev, dst, nbytes, DMA_BIDIRECTIONAL,
|
|
|
|
&req_ctx->out_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
|
|
|
|
&dummy, &mapped_nents);
|
|
|
|
if (rc)
|
2018-01-22 17:27:01 +08:00
|
|
|
goto cipher_exit;
|
|
|
|
if (mapped_nents > 1)
|
|
|
|
req_ctx->dma_buf_type = CC_DMA_BUF_MLLI;
|
|
|
|
|
|
|
|
if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
|
|
|
|
cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src,
|
|
|
|
nbytes, 0, true,
|
|
|
|
&req_ctx->in_mlli_nents);
|
|
|
|
cc_add_sg_entry(dev, &sg_data, req_ctx->out_nents, dst,
|
|
|
|
nbytes, 0, true,
|
|
|
|
&req_ctx->out_mlli_nents);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
|
2020-02-12 02:19:14 +08:00
|
|
|
mlli_params->curr_pool = drvdata->mlli_buffs_pool;
|
2018-01-22 17:27:01 +08:00
|
|
|
rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
|
|
|
|
if (rc)
|
|
|
|
goto cipher_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(dev, "areq_ctx->dma_buf_type = %s\n",
|
|
|
|
cc_dma_buf_type(req_ctx->dma_buf_type));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cipher_exit:
|
|
|
|
cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2018-01-22 17:27:03 +08:00
|
|
|
void cc_unmap_aead_request(struct device *dev, struct aead_request *req)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
unsigned int hw_iv_size = areq_ctx->hw_iv_size;
|
|
|
|
struct cc_drvdata *drvdata = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (areq_ctx->mac_buf_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->mac_buf_dma_addr,
|
|
|
|
MAX_MAC_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) {
|
|
|
|
if (areq_ctx->hkey_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->hkey_dma_addr,
|
|
|
|
AES_BLOCK_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->gcm_block_len_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->gcm_block_len_dma_addr,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->gcm_iv_inc1_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->gcm_iv_inc1_dma_addr,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->gcm_iv_inc2_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->gcm_iv_inc2_dma_addr,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
|
|
|
|
if (areq_ctx->ccm_iv0_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->ccm_iv0_dma_addr,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_unmap_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
if (areq_ctx->gen_ctx.iv_dma_addr) {
|
|
|
|
dma_unmap_single(dev, areq_ctx->gen_ctx.iv_dma_addr,
|
|
|
|
hw_iv_size, DMA_BIDIRECTIONAL);
|
2020-08-07 14:18:13 +08:00
|
|
|
kfree_sensitive(areq_ctx->gen_ctx.iv);
|
2018-01-22 17:27:03 +08:00
|
|
|
}
|
|
|
|
|
2019-01-15 21:43:13 +08:00
|
|
|
/* Release pool */
|
|
|
|
if ((areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI ||
|
|
|
|
areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) &&
|
|
|
|
(areq_ctx->mlli_params.mlli_virt_addr)) {
|
2018-01-22 17:27:03 +08:00
|
|
|
dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n",
|
|
|
|
&areq_ctx->mlli_params.mlli_dma_addr,
|
|
|
|
areq_ctx->mlli_params.mlli_virt_addr);
|
|
|
|
dma_pool_free(areq_ctx->mlli_params.curr_pool,
|
|
|
|
areq_ctx->mlli_params.mlli_virt_addr,
|
|
|
|
areq_ctx->mlli_params.mlli_dma_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(dev, "Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n",
|
|
|
|
sg_virt(req->src), areq_ctx->src.nents, areq_ctx->assoc.nents,
|
2019-04-18 21:38:59 +08:00
|
|
|
areq_ctx->assoclen, req->cryptlen);
|
2018-01-22 17:27:03 +08:00
|
|
|
|
2020-01-29 22:37:54 +08:00
|
|
|
dma_unmap_sg(dev, req->src, areq_ctx->src.mapped_nents,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2018-01-22 17:27:03 +08:00
|
|
|
if (req->src != req->dst) {
|
|
|
|
dev_dbg(dev, "Unmapping dst sgl: req->dst=%pK\n",
|
|
|
|
sg_virt(req->dst));
|
2020-01-29 22:37:54 +08:00
|
|
|
dma_unmap_sg(dev, req->dst, areq_ctx->dst.mapped_nents,
|
2018-01-22 17:27:03 +08:00
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
if (drvdata->coherent &&
|
|
|
|
areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT &&
|
|
|
|
req->src == req->dst) {
|
|
|
|
/* copy back mac from temporary location to deal with possible
|
|
|
|
* data memory overriding that caused by cache coherence
|
|
|
|
* problem.
|
|
|
|
*/
|
|
|
|
cc_copy_mac(dev, req, CC_SG_FROM_BUF);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-18 21:38:57 +08:00
|
|
|
static bool cc_is_icv_frag(unsigned int sgl_nents, unsigned int authsize,
|
|
|
|
u32 last_entry_data_size)
|
2018-01-22 17:27:03 +08:00
|
|
|
{
|
2019-04-18 21:38:57 +08:00
|
|
|
return ((sgl_nents > 1) && (last_entry_data_size < authsize));
|
2018-01-22 17:27:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int cc_aead_chain_iv(struct cc_drvdata *drvdata,
|
|
|
|
struct aead_request *req,
|
|
|
|
struct buffer_array *sg_data,
|
|
|
|
bool is_last, bool do_chain)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
unsigned int hw_iv_size = areq_ctx->hw_iv_size;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
2019-04-18 21:39:05 +08:00
|
|
|
gfp_t flags = cc_gfp_flags(&req->base);
|
2018-01-22 17:27:03 +08:00
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
if (!req->iv) {
|
|
|
|
areq_ctx->gen_ctx.iv_dma_addr = 0;
|
2019-04-18 21:39:05 +08:00
|
|
|
areq_ctx->gen_ctx.iv = NULL;
|
2018-01-22 17:27:03 +08:00
|
|
|
goto chain_iv_exit;
|
|
|
|
}
|
|
|
|
|
2019-04-18 21:39:05 +08:00
|
|
|
areq_ctx->gen_ctx.iv = kmemdup(req->iv, hw_iv_size, flags);
|
|
|
|
if (!areq_ctx->gen_ctx.iv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
areq_ctx->gen_ctx.iv_dma_addr =
|
|
|
|
dma_map_single(dev, areq_ctx->gen_ctx.iv, hw_iv_size,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2018-01-22 17:27:03 +08:00
|
|
|
if (dma_mapping_error(dev, areq_ctx->gen_ctx.iv_dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n",
|
|
|
|
hw_iv_size, req->iv);
|
2020-08-07 14:18:13 +08:00
|
|
|
kfree_sensitive(areq_ctx->gen_ctx.iv);
|
2019-04-18 21:39:05 +08:00
|
|
|
areq_ctx->gen_ctx.iv = NULL;
|
2018-01-22 17:27:03 +08:00
|
|
|
rc = -ENOMEM;
|
|
|
|
goto chain_iv_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n",
|
|
|
|
hw_iv_size, req->iv, &areq_ctx->gen_ctx.iv_dma_addr);
|
|
|
|
|
|
|
|
chain_iv_exit:
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cc_aead_chain_assoc(struct cc_drvdata *drvdata,
|
|
|
|
struct aead_request *req,
|
|
|
|
struct buffer_array *sg_data,
|
|
|
|
bool is_last, bool do_chain)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
int rc = 0;
|
2019-04-18 21:39:00 +08:00
|
|
|
int mapped_nents = 0;
|
2018-01-22 17:27:03 +08:00
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
|
|
|
|
if (!sg_data) {
|
|
|
|
rc = -EINVAL;
|
|
|
|
goto chain_assoc_exit;
|
|
|
|
}
|
|
|
|
|
2019-04-18 21:38:59 +08:00
|
|
|
if (areq_ctx->assoclen == 0) {
|
2018-01-22 17:27:03 +08:00
|
|
|
areq_ctx->assoc_buff_type = CC_DMA_BUF_NULL;
|
|
|
|
areq_ctx->assoc.nents = 0;
|
|
|
|
areq_ctx->assoc.mlli_nents = 0;
|
|
|
|
dev_dbg(dev, "Chain assoc of length 0: buff_type=%s nents=%u\n",
|
|
|
|
cc_dma_buf_type(areq_ctx->assoc_buff_type),
|
|
|
|
areq_ctx->assoc.nents);
|
|
|
|
goto chain_assoc_exit;
|
|
|
|
}
|
|
|
|
|
2020-03-08 23:57:09 +08:00
|
|
|
mapped_nents = sg_nents_for_len(req->src, areq_ctx->assoclen);
|
2019-04-18 21:39:00 +08:00
|
|
|
if (mapped_nents < 0)
|
|
|
|
return mapped_nents;
|
|
|
|
|
2018-01-22 17:27:03 +08:00
|
|
|
if (mapped_nents > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) {
|
|
|
|
dev_err(dev, "Too many fragments. current %d max %d\n",
|
|
|
|
mapped_nents, LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
areq_ctx->assoc.nents = mapped_nents;
|
|
|
|
|
|
|
|
/* in CCM case we have additional entry for
|
|
|
|
* ccm header configurations
|
|
|
|
*/
|
|
|
|
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
|
|
|
|
if ((mapped_nents + 1) > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) {
|
|
|
|
dev_err(dev, "CCM case.Too many fragments. Current %d max %d\n",
|
|
|
|
(areq_ctx->assoc.nents + 1),
|
|
|
|
LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES);
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto chain_assoc_exit;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mapped_nents == 1 && areq_ctx->ccm_hdr_size == ccm_header_size_null)
|
|
|
|
areq_ctx->assoc_buff_type = CC_DMA_BUF_DLLI;
|
|
|
|
else
|
|
|
|
areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI;
|
|
|
|
|
|
|
|
if (do_chain || areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) {
|
|
|
|
dev_dbg(dev, "Chain assoc: buff_type=%s nents=%u\n",
|
|
|
|
cc_dma_buf_type(areq_ctx->assoc_buff_type),
|
|
|
|
areq_ctx->assoc.nents);
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->assoc.nents, req->src,
|
2019-04-18 21:38:59 +08:00
|
|
|
areq_ctx->assoclen, 0, is_last,
|
2018-01-22 17:27:03 +08:00
|
|
|
&areq_ctx->assoc.mlli_nents);
|
|
|
|
areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI;
|
|
|
|
}
|
|
|
|
|
|
|
|
chain_assoc_exit:
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cc_prepare_aead_data_dlli(struct aead_request *req,
|
|
|
|
u32 *src_last_bytes, u32 *dst_last_bytes)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
|
|
|
|
unsigned int authsize = areq_ctx->req_authsize;
|
2019-04-18 21:38:58 +08:00
|
|
|
struct scatterlist *sg;
|
|
|
|
ssize_t offset;
|
2018-01-22 17:27:03 +08:00
|
|
|
|
|
|
|
areq_ctx->is_icv_fragmented = false;
|
2019-04-18 21:38:58 +08:00
|
|
|
|
|
|
|
if ((req->src == req->dst) || direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
|
|
|
|
sg = areq_ctx->src_sgl;
|
|
|
|
offset = *src_last_bytes - authsize;
|
2018-01-22 17:27:03 +08:00
|
|
|
} else {
|
2019-04-18 21:38:58 +08:00
|
|
|
sg = areq_ctx->dst_sgl;
|
|
|
|
offset = *dst_last_bytes - authsize;
|
2018-01-22 17:27:03 +08:00
|
|
|
}
|
2019-04-18 21:38:58 +08:00
|
|
|
|
|
|
|
areq_ctx->icv_dma_addr = sg_dma_address(sg) + offset;
|
|
|
|
areq_ctx->icv_virt_addr = sg_virt(sg) + offset;
|
2018-01-22 17:27:03 +08:00
|
|
|
}
|
|
|
|
|
2019-04-18 21:38:57 +08:00
|
|
|
static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
|
|
|
|
struct aead_request *req,
|
|
|
|
struct buffer_array *sg_data,
|
|
|
|
u32 *src_last_bytes, u32 *dst_last_bytes,
|
|
|
|
bool is_last_table)
|
2018-01-22 17:27:03 +08:00
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
|
|
|
|
unsigned int authsize = areq_ctx->req_authsize;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
struct scatterlist *sg;
|
|
|
|
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
/*INPLACE*/
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
|
|
|
|
areq_ctx->src_sgl, areq_ctx->cryptlen,
|
|
|
|
areq_ctx->src_offset, is_last_table,
|
|
|
|
&areq_ctx->src.mlli_nents);
|
|
|
|
|
2019-04-18 21:38:57 +08:00
|
|
|
areq_ctx->is_icv_fragmented =
|
|
|
|
cc_is_icv_frag(areq_ctx->src.nents, authsize,
|
|
|
|
*src_last_bytes);
|
2018-01-22 17:27:03 +08:00
|
|
|
|
|
|
|
if (areq_ctx->is_icv_fragmented) {
|
|
|
|
/* Backup happens only when ICV is fragmented, ICV
|
|
|
|
* verification is made by CPU compare in order to
|
|
|
|
* simplify MAC verification upon request completion
|
|
|
|
*/
|
|
|
|
if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
|
|
|
|
/* In coherent platforms (e.g. ACP)
|
|
|
|
* already copying ICV for any
|
|
|
|
* INPLACE-DECRYPT operation, hence
|
|
|
|
* we must neglect this code.
|
|
|
|
*/
|
|
|
|
if (!drvdata->coherent)
|
|
|
|
cc_copy_mac(dev, req, CC_SG_TO_BUF);
|
|
|
|
|
|
|
|
areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
|
|
|
|
} else {
|
|
|
|
areq_ctx->icv_virt_addr = areq_ctx->mac_buf;
|
|
|
|
areq_ctx->icv_dma_addr =
|
|
|
|
areq_ctx->mac_buf_dma_addr;
|
|
|
|
}
|
|
|
|
} else { /* Contig. ICV */
|
|
|
|
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
|
|
|
|
/*Should hanlde if the sg is not contig.*/
|
|
|
|
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
|
|
|
|
(*src_last_bytes - authsize);
|
|
|
|
areq_ctx->icv_virt_addr = sg_virt(sg) +
|
|
|
|
(*src_last_bytes - authsize);
|
|
|
|
}
|
|
|
|
|
|
|
|
} else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
|
|
|
|
/*NON-INPLACE and DECRYPT*/
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
|
|
|
|
areq_ctx->src_sgl, areq_ctx->cryptlen,
|
|
|
|
areq_ctx->src_offset, is_last_table,
|
|
|
|
&areq_ctx->src.mlli_nents);
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->dst.nents,
|
|
|
|
areq_ctx->dst_sgl, areq_ctx->cryptlen,
|
|
|
|
areq_ctx->dst_offset, is_last_table,
|
|
|
|
&areq_ctx->dst.mlli_nents);
|
|
|
|
|
2019-04-18 21:38:57 +08:00
|
|
|
areq_ctx->is_icv_fragmented =
|
|
|
|
cc_is_icv_frag(areq_ctx->src.nents, authsize,
|
|
|
|
*src_last_bytes);
|
2018-01-22 17:27:03 +08:00
|
|
|
/* Backup happens only when ICV is fragmented, ICV
|
2019-04-18 21:38:57 +08:00
|
|
|
|
2018-01-22 17:27:03 +08:00
|
|
|
* verification is made by CPU compare in order to simplify
|
|
|
|
* MAC verification upon request completion
|
|
|
|
*/
|
|
|
|
if (areq_ctx->is_icv_fragmented) {
|
|
|
|
cc_copy_mac(dev, req, CC_SG_TO_BUF);
|
|
|
|
areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
|
|
|
|
|
|
|
|
} else { /* Contig. ICV */
|
|
|
|
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
|
|
|
|
/*Should hanlde if the sg is not contig.*/
|
|
|
|
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
|
|
|
|
(*src_last_bytes - authsize);
|
|
|
|
areq_ctx->icv_virt_addr = sg_virt(sg) +
|
|
|
|
(*src_last_bytes - authsize);
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/*NON-INPLACE and ENCRYPT*/
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->dst.nents,
|
|
|
|
areq_ctx->dst_sgl, areq_ctx->cryptlen,
|
|
|
|
areq_ctx->dst_offset, is_last_table,
|
|
|
|
&areq_ctx->dst.mlli_nents);
|
|
|
|
cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
|
|
|
|
areq_ctx->src_sgl, areq_ctx->cryptlen,
|
|
|
|
areq_ctx->src_offset, is_last_table,
|
|
|
|
&areq_ctx->src.mlli_nents);
|
|
|
|
|
2019-04-18 21:38:57 +08:00
|
|
|
areq_ctx->is_icv_fragmented =
|
|
|
|
cc_is_icv_frag(areq_ctx->dst.nents, authsize,
|
|
|
|
*dst_last_bytes);
|
2018-01-22 17:27:03 +08:00
|
|
|
|
|
|
|
if (!areq_ctx->is_icv_fragmented) {
|
|
|
|
sg = &areq_ctx->dst_sgl[areq_ctx->dst.nents - 1];
|
|
|
|
/* Contig. ICV */
|
|
|
|
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
|
|
|
|
(*dst_last_bytes - authsize);
|
|
|
|
areq_ctx->icv_virt_addr = sg_virt(sg) +
|
|
|
|
(*dst_last_bytes - authsize);
|
|
|
|
} else {
|
|
|
|
areq_ctx->icv_dma_addr = areq_ctx->mac_buf_dma_addr;
|
|
|
|
areq_ctx->icv_virt_addr = areq_ctx->mac_buf;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cc_aead_chain_data(struct cc_drvdata *drvdata,
|
|
|
|
struct aead_request *req,
|
|
|
|
struct buffer_array *sg_data,
|
|
|
|
bool is_last_table, bool do_chain)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
|
|
|
|
unsigned int authsize = areq_ctx->req_authsize;
|
|
|
|
unsigned int src_last_bytes = 0, dst_last_bytes = 0;
|
|
|
|
int rc = 0;
|
|
|
|
u32 src_mapped_nents = 0, dst_mapped_nents = 0;
|
|
|
|
u32 offset = 0;
|
|
|
|
/* non-inplace mode */
|
2020-03-08 23:57:09 +08:00
|
|
|
unsigned int size_for_map = req->assoclen + req->cryptlen;
|
2018-01-22 17:27:03 +08:00
|
|
|
u32 sg_index = 0;
|
2020-03-08 23:57:09 +08:00
|
|
|
u32 size_to_skip = req->assoclen;
|
2019-04-18 21:39:00 +08:00
|
|
|
struct scatterlist *sgl;
|
2018-01-22 17:27:03 +08:00
|
|
|
|
|
|
|
offset = size_to_skip;
|
|
|
|
|
|
|
|
if (!sg_data)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
areq_ctx->src_sgl = req->src;
|
|
|
|
areq_ctx->dst_sgl = req->dst;
|
|
|
|
|
|
|
|
size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
|
|
|
|
authsize : 0;
|
|
|
|
src_mapped_nents = cc_get_sgl_nents(dev, req->src, size_for_map,
|
2019-04-18 21:38:48 +08:00
|
|
|
&src_last_bytes);
|
2018-01-22 17:27:03 +08:00
|
|
|
sg_index = areq_ctx->src_sgl->length;
|
|
|
|
//check where the data starts
|
2020-01-29 22:37:54 +08:00
|
|
|
while (src_mapped_nents && (sg_index <= size_to_skip)) {
|
2019-04-18 21:39:00 +08:00
|
|
|
src_mapped_nents--;
|
2018-01-22 17:27:03 +08:00
|
|
|
offset -= areq_ctx->src_sgl->length;
|
2019-04-18 21:39:00 +08:00
|
|
|
sgl = sg_next(areq_ctx->src_sgl);
|
|
|
|
if (!sgl)
|
|
|
|
break;
|
|
|
|
areq_ctx->src_sgl = sgl;
|
2018-01-22 17:27:03 +08:00
|
|
|
sg_index += areq_ctx->src_sgl->length;
|
|
|
|
}
|
|
|
|
if (src_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES) {
|
|
|
|
dev_err(dev, "Too many fragments. current %d max %d\n",
|
|
|
|
src_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
areq_ctx->src.nents = src_mapped_nents;
|
|
|
|
|
|
|
|
areq_ctx->src_offset = offset;
|
|
|
|
|
|
|
|
if (req->src != req->dst) {
|
2020-03-08 23:57:09 +08:00
|
|
|
size_for_map = req->assoclen + req->cryptlen;
|
2020-02-03 00:19:14 +08:00
|
|
|
|
|
|
|
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT)
|
|
|
|
size_for_map += authsize;
|
|
|
|
else
|
|
|
|
size_for_map -= authsize;
|
|
|
|
|
2018-01-22 17:27:03 +08:00
|
|
|
rc = cc_map_sg(dev, req->dst, size_for_map, DMA_BIDIRECTIONAL,
|
2020-01-29 22:37:54 +08:00
|
|
|
&areq_ctx->dst.mapped_nents,
|
2018-01-22 17:27:03 +08:00
|
|
|
LLI_MAX_NUM_OF_DATA_ENTRIES, &dst_last_bytes,
|
|
|
|
&dst_mapped_nents);
|
2019-01-15 21:43:11 +08:00
|
|
|
if (rc)
|
2018-01-22 17:27:03 +08:00
|
|
|
goto chain_data_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
dst_mapped_nents = cc_get_sgl_nents(dev, req->dst, size_for_map,
|
2019-04-18 21:38:48 +08:00
|
|
|
&dst_last_bytes);
|
2018-01-22 17:27:03 +08:00
|
|
|
sg_index = areq_ctx->dst_sgl->length;
|
|
|
|
offset = size_to_skip;
|
|
|
|
|
|
|
|
//check where the data starts
|
2020-01-29 22:37:54 +08:00
|
|
|
while (dst_mapped_nents && sg_index <= size_to_skip) {
|
2019-04-18 21:39:00 +08:00
|
|
|
dst_mapped_nents--;
|
2018-01-22 17:27:03 +08:00
|
|
|
offset -= areq_ctx->dst_sgl->length;
|
2019-04-18 21:39:00 +08:00
|
|
|
sgl = sg_next(areq_ctx->dst_sgl);
|
|
|
|
if (!sgl)
|
|
|
|
break;
|
|
|
|
areq_ctx->dst_sgl = sgl;
|
2018-01-22 17:27:03 +08:00
|
|
|
sg_index += areq_ctx->dst_sgl->length;
|
|
|
|
}
|
|
|
|
if (dst_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES) {
|
|
|
|
dev_err(dev, "Too many fragments. current %d max %d\n",
|
|
|
|
dst_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
areq_ctx->dst.nents = dst_mapped_nents;
|
|
|
|
areq_ctx->dst_offset = offset;
|
|
|
|
if (src_mapped_nents > 1 ||
|
|
|
|
dst_mapped_nents > 1 ||
|
|
|
|
do_chain) {
|
|
|
|
areq_ctx->data_buff_type = CC_DMA_BUF_MLLI;
|
2019-04-18 21:38:57 +08:00
|
|
|
cc_prepare_aead_data_mlli(drvdata, req, sg_data,
|
|
|
|
&src_last_bytes, &dst_last_bytes,
|
|
|
|
is_last_table);
|
2018-01-22 17:27:03 +08:00
|
|
|
} else {
|
|
|
|
areq_ctx->data_buff_type = CC_DMA_BUF_DLLI;
|
|
|
|
cc_prepare_aead_data_dlli(req, &src_last_bytes,
|
|
|
|
&dst_last_bytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
chain_data_exit:
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cc_update_aead_mlli_nents(struct cc_drvdata *drvdata,
|
|
|
|
struct aead_request *req)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
u32 curr_mlli_size = 0;
|
|
|
|
|
|
|
|
if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) {
|
|
|
|
areq_ctx->assoc.sram_addr = drvdata->mlli_sram_addr;
|
|
|
|
curr_mlli_size = areq_ctx->assoc.mlli_nents *
|
|
|
|
LLI_ENTRY_BYTE_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) {
|
|
|
|
/*Inplace case dst nents equal to src nents*/
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
areq_ctx->dst.mlli_nents = areq_ctx->src.mlli_nents;
|
|
|
|
areq_ctx->src.sram_addr = drvdata->mlli_sram_addr +
|
|
|
|
curr_mlli_size;
|
|
|
|
areq_ctx->dst.sram_addr = areq_ctx->src.sram_addr;
|
|
|
|
if (!areq_ctx->is_single_pass)
|
|
|
|
areq_ctx->assoc.mlli_nents +=
|
|
|
|
areq_ctx->src.mlli_nents;
|
|
|
|
} else {
|
|
|
|
if (areq_ctx->gen_ctx.op_type ==
|
|
|
|
DRV_CRYPTO_DIRECTION_DECRYPT) {
|
|
|
|
areq_ctx->src.sram_addr =
|
|
|
|
drvdata->mlli_sram_addr +
|
|
|
|
curr_mlli_size;
|
|
|
|
areq_ctx->dst.sram_addr =
|
|
|
|
areq_ctx->src.sram_addr +
|
|
|
|
areq_ctx->src.mlli_nents *
|
|
|
|
LLI_ENTRY_BYTE_SIZE;
|
|
|
|
if (!areq_ctx->is_single_pass)
|
|
|
|
areq_ctx->assoc.mlli_nents +=
|
|
|
|
areq_ctx->src.mlli_nents;
|
|
|
|
} else {
|
|
|
|
areq_ctx->dst.sram_addr =
|
|
|
|
drvdata->mlli_sram_addr +
|
|
|
|
curr_mlli_size;
|
|
|
|
areq_ctx->src.sram_addr =
|
|
|
|
areq_ctx->dst.sram_addr +
|
|
|
|
areq_ctx->dst.mlli_nents *
|
|
|
|
LLI_ENTRY_BYTE_SIZE;
|
|
|
|
if (!areq_ctx->is_single_pass)
|
|
|
|
areq_ctx->assoc.mlli_nents +=
|
|
|
|
areq_ctx->dst.mlli_nents;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req)
|
|
|
|
{
|
|
|
|
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
|
|
|
|
struct mlli_params *mlli_params = &areq_ctx->mlli_params;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
struct buffer_array sg_data;
|
|
|
|
unsigned int authsize = areq_ctx->req_authsize;
|
|
|
|
int rc = 0;
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
u32 mapped_nents = 0;
|
|
|
|
u32 dummy = 0; /*used for the assoc data fragments */
|
2020-03-08 23:57:09 +08:00
|
|
|
u32 size_to_map;
|
2018-01-22 17:27:03 +08:00
|
|
|
gfp_t flags = cc_gfp_flags(&req->base);
|
|
|
|
|
|
|
|
mlli_params->curr_pool = NULL;
|
|
|
|
sg_data.num_of_buffers = 0;
|
|
|
|
|
|
|
|
/* copy mac to a temporary location to deal with possible
|
|
|
|
* data memory overriding that caused by cache coherence problem.
|
|
|
|
*/
|
|
|
|
if (drvdata->coherent &&
|
|
|
|
areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT &&
|
|
|
|
req->src == req->dst)
|
|
|
|
cc_copy_mac(dev, req, CC_SG_TO_BUF);
|
|
|
|
|
|
|
|
/* cacluate the size for cipher remove ICV in decrypt*/
|
|
|
|
areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type ==
|
|
|
|
DRV_CRYPTO_DIRECTION_ENCRYPT) ?
|
|
|
|
req->cryptlen :
|
|
|
|
(req->cryptlen - authsize);
|
|
|
|
|
|
|
|
dma_addr = dma_map_single(dev, areq_ctx->mac_buf, MAX_MAC_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n",
|
|
|
|
MAX_MAC_SIZE, areq_ctx->mac_buf);
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->mac_buf_dma_addr = dma_addr;
|
|
|
|
|
|
|
|
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
|
|
|
|
void *addr = areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET;
|
|
|
|
|
|
|
|
dma_addr = dma_map_single(dev, addr, AES_BLOCK_SIZE,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n",
|
|
|
|
AES_BLOCK_SIZE, addr);
|
|
|
|
areq_ctx->ccm_iv0_dma_addr = 0;
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->ccm_iv0_dma_addr = dma_addr;
|
|
|
|
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_set_aead_conf_buf(dev, areq_ctx, areq_ctx->ccm_config,
|
2019-04-18 21:38:59 +08:00
|
|
|
&sg_data, areq_ctx->assoclen);
|
2019-01-15 21:43:11 +08:00
|
|
|
if (rc)
|
2018-01-22 17:27:03 +08:00
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) {
|
|
|
|
dma_addr = dma_map_single(dev, areq_ctx->hkey, AES_BLOCK_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping hkey %u B at va=%pK for DMA failed\n",
|
|
|
|
AES_BLOCK_SIZE, areq_ctx->hkey);
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->hkey_dma_addr = dma_addr;
|
|
|
|
|
|
|
|
dma_addr = dma_map_single(dev, &areq_ctx->gcm_len_block,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping gcm_len_block %u B at va=%pK for DMA failed\n",
|
|
|
|
AES_BLOCK_SIZE, &areq_ctx->gcm_len_block);
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->gcm_block_len_dma_addr = dma_addr;
|
|
|
|
|
|
|
|
dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc1,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping gcm_iv_inc1 %u B at va=%pK for DMA failed\n",
|
|
|
|
AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc1));
|
|
|
|
areq_ctx->gcm_iv_inc1_dma_addr = 0;
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->gcm_iv_inc1_dma_addr = dma_addr;
|
|
|
|
|
|
|
|
dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc2,
|
|
|
|
AES_BLOCK_SIZE, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (dma_mapping_error(dev, dma_addr)) {
|
|
|
|
dev_err(dev, "Mapping gcm_iv_inc2 %u B at va=%pK for DMA failed\n",
|
|
|
|
AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc2));
|
|
|
|
areq_ctx->gcm_iv_inc2_dma_addr = 0;
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
areq_ctx->gcm_iv_inc2_dma_addr = dma_addr;
|
|
|
|
}
|
|
|
|
|
2020-03-08 23:57:09 +08:00
|
|
|
size_to_map = req->cryptlen + req->assoclen;
|
2020-01-29 22:37:55 +08:00
|
|
|
/* If we do in-place encryption, we also need the auth tag */
|
|
|
|
if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) &&
|
|
|
|
(req->src == req->dst)) {
|
2018-01-22 17:27:03 +08:00
|
|
|
size_to_map += authsize;
|
2020-01-29 22:37:55 +08:00
|
|
|
}
|
2020-03-08 23:57:09 +08:00
|
|
|
|
2018-01-22 17:27:03 +08:00
|
|
|
rc = cc_map_sg(dev, req->src, size_to_map, DMA_BIDIRECTIONAL,
|
2020-01-29 22:37:54 +08:00
|
|
|
&areq_ctx->src.mapped_nents,
|
2018-01-22 17:27:03 +08:00
|
|
|
(LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES +
|
|
|
|
LLI_MAX_NUM_OF_DATA_ENTRIES),
|
|
|
|
&dummy, &mapped_nents);
|
2019-01-15 21:43:11 +08:00
|
|
|
if (rc)
|
2018-01-22 17:27:03 +08:00
|
|
|
goto aead_map_failure;
|
|
|
|
|
|
|
|
if (areq_ctx->is_single_pass) {
|
|
|
|
/*
|
|
|
|
* Create MLLI table for:
|
|
|
|
* (1) Assoc. data
|
|
|
|
* (2) Src/Dst SGLs
|
|
|
|
* Note: IV is contg. buffer (not an SGL)
|
|
|
|
*/
|
|
|
|
rc = cc_aead_chain_assoc(drvdata, req, &sg_data, true, false);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
rc = cc_aead_chain_iv(drvdata, req, &sg_data, true, false);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
rc = cc_aead_chain_data(drvdata, req, &sg_data, true, false);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
} else { /* DOUBLE-PASS flow */
|
|
|
|
/*
|
|
|
|
* Prepare MLLI table(s) in this order:
|
|
|
|
*
|
|
|
|
* If ENCRYPT/DECRYPT (inplace):
|
|
|
|
* (1) MLLI table for assoc
|
|
|
|
* (2) IV entry (chained right after end of assoc)
|
|
|
|
* (3) MLLI for src/dst (inplace operation)
|
|
|
|
*
|
|
|
|
* If ENCRYPT (non-inplace)
|
|
|
|
* (1) MLLI table for assoc
|
|
|
|
* (2) IV entry (chained right after end of assoc)
|
|
|
|
* (3) MLLI for dst
|
|
|
|
* (4) MLLI for src
|
|
|
|
*
|
|
|
|
* If DECRYPT (non-inplace)
|
|
|
|
* (1) MLLI table for assoc
|
|
|
|
* (2) IV entry (chained right after end of assoc)
|
|
|
|
* (3) MLLI for src
|
|
|
|
* (4) MLLI for dst
|
|
|
|
*/
|
|
|
|
rc = cc_aead_chain_assoc(drvdata, req, &sg_data, false, true);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
rc = cc_aead_chain_iv(drvdata, req, &sg_data, false, true);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
rc = cc_aead_chain_data(drvdata, req, &sg_data, true, true);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mlli support -start building the MLLI according to the above
|
|
|
|
* results
|
|
|
|
*/
|
|
|
|
if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI ||
|
|
|
|
areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) {
|
2020-02-12 02:19:14 +08:00
|
|
|
mlli_params->curr_pool = drvdata->mlli_buffs_pool;
|
2018-01-22 17:27:03 +08:00
|
|
|
rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
|
|
|
|
if (rc)
|
|
|
|
goto aead_map_failure;
|
|
|
|
|
|
|
|
cc_update_aead_mlli_nents(drvdata, req);
|
|
|
|
dev_dbg(dev, "assoc params mn %d\n",
|
|
|
|
areq_ctx->assoc.mlli_nents);
|
|
|
|
dev_dbg(dev, "src params mn %d\n", areq_ctx->src.mlli_nents);
|
|
|
|
dev_dbg(dev, "dst params mn %d\n", areq_ctx->dst.mlli_nents);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
aead_map_failure:
|
|
|
|
cc_unmap_aead_request(dev, req);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2018-01-22 17:27:02 +08:00
|
|
|
int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx,
|
|
|
|
struct scatterlist *src, unsigned int nbytes,
|
|
|
|
bool do_update, gfp_t flags)
|
|
|
|
{
|
|
|
|
struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
u8 *curr_buff = cc_hash_buf(areq_ctx);
|
|
|
|
u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
|
|
|
|
struct mlli_params *mlli_params = &areq_ctx->mlli_params;
|
|
|
|
struct buffer_array sg_data;
|
2019-01-15 21:43:11 +08:00
|
|
|
int rc = 0;
|
2018-01-22 17:27:02 +08:00
|
|
|
u32 dummy = 0;
|
|
|
|
u32 mapped_nents = 0;
|
|
|
|
|
|
|
|
dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X src=%pK curr_index=%u\n",
|
|
|
|
curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
|
|
|
|
/* Init the type of the dma buffer */
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
|
|
|
|
mlli_params->curr_pool = NULL;
|
|
|
|
sg_data.num_of_buffers = 0;
|
|
|
|
areq_ctx->in_nents = 0;
|
|
|
|
|
|
|
|
if (nbytes == 0 && *curr_buff_cnt == 0) {
|
|
|
|
/* nothing to do */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* map the previous buffer */
|
|
|
|
if (*curr_buff_cnt) {
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
|
|
|
|
&sg_data);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2018-01-22 17:27:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (src && nbytes > 0 && do_update) {
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_map_sg(dev, src, nbytes, DMA_TO_DEVICE,
|
|
|
|
&areq_ctx->in_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
|
|
|
|
&dummy, &mapped_nents);
|
|
|
|
if (rc)
|
2018-01-22 17:27:02 +08:00
|
|
|
goto unmap_curr_buff;
|
|
|
|
if (src && mapped_nents == 1 &&
|
|
|
|
areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
|
|
|
|
memcpy(areq_ctx->buff_sg, src,
|
|
|
|
sizeof(struct scatterlist));
|
|
|
|
areq_ctx->buff_sg->length = nbytes;
|
|
|
|
areq_ctx->curr_sg = areq_ctx->buff_sg;
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
|
|
|
|
} else {
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*build mlli */
|
|
|
|
if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
|
2020-02-12 02:19:14 +08:00
|
|
|
mlli_params->curr_pool = drvdata->mlli_buffs_pool;
|
2018-01-22 17:27:02 +08:00
|
|
|
/* add the src data to the sg_data */
|
|
|
|
cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src, nbytes,
|
|
|
|
0, true, &areq_ctx->mlli_nents);
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
|
|
|
|
if (rc)
|
2018-01-22 17:27:02 +08:00
|
|
|
goto fail_unmap_din;
|
|
|
|
}
|
|
|
|
/* change the buffer index for the unmap function */
|
|
|
|
areq_ctx->buff_index = (areq_ctx->buff_index ^ 1);
|
|
|
|
dev_dbg(dev, "areq_ctx->data_dma_buf_type = %s\n",
|
|
|
|
cc_dma_buf_type(areq_ctx->data_dma_buf_type));
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail_unmap_din:
|
|
|
|
dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
unmap_curr_buff:
|
|
|
|
if (*curr_buff_cnt)
|
|
|
|
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
|
|
|
|
|
2019-01-15 21:43:11 +08:00
|
|
|
return rc;
|
2018-01-22 17:27:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx,
|
|
|
|
struct scatterlist *src, unsigned int nbytes,
|
|
|
|
unsigned int block_size, gfp_t flags)
|
|
|
|
{
|
|
|
|
struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
u8 *curr_buff = cc_hash_buf(areq_ctx);
|
|
|
|
u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
|
|
|
|
u8 *next_buff = cc_next_buf(areq_ctx);
|
|
|
|
u32 *next_buff_cnt = cc_next_buf_cnt(areq_ctx);
|
|
|
|
struct mlli_params *mlli_params = &areq_ctx->mlli_params;
|
|
|
|
unsigned int update_data_len;
|
|
|
|
u32 total_in_len = nbytes + *curr_buff_cnt;
|
|
|
|
struct buffer_array sg_data;
|
|
|
|
unsigned int swap_index = 0;
|
2019-01-15 21:43:11 +08:00
|
|
|
int rc = 0;
|
2018-01-22 17:27:02 +08:00
|
|
|
u32 dummy = 0;
|
|
|
|
u32 mapped_nents = 0;
|
|
|
|
|
|
|
|
dev_dbg(dev, " update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X src=%pK curr_index=%u\n",
|
|
|
|
curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
|
|
|
|
/* Init the type of the dma buffer */
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
|
|
|
|
mlli_params->curr_pool = NULL;
|
|
|
|
areq_ctx->curr_sg = NULL;
|
|
|
|
sg_data.num_of_buffers = 0;
|
|
|
|
areq_ctx->in_nents = 0;
|
|
|
|
|
|
|
|
if (total_in_len < block_size) {
|
|
|
|
dev_dbg(dev, " less than one block: curr_buff=%pK *curr_buff_cnt=0x%X copy_to=%pK\n",
|
|
|
|
curr_buff, *curr_buff_cnt, &curr_buff[*curr_buff_cnt]);
|
2019-04-18 21:38:52 +08:00
|
|
|
areq_ctx->in_nents = sg_nents_for_len(src, nbytes);
|
2018-01-22 17:27:02 +08:00
|
|
|
sg_copy_to_buffer(src, areq_ctx->in_nents,
|
|
|
|
&curr_buff[*curr_buff_cnt], nbytes);
|
|
|
|
*curr_buff_cnt += nbytes;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate the residue size*/
|
|
|
|
*next_buff_cnt = total_in_len & (block_size - 1);
|
|
|
|
/* update data len */
|
|
|
|
update_data_len = total_in_len - *next_buff_cnt;
|
|
|
|
|
|
|
|
dev_dbg(dev, " temp length : *next_buff_cnt=0x%X update_data_len=0x%X\n",
|
|
|
|
*next_buff_cnt, update_data_len);
|
|
|
|
|
|
|
|
/* Copy the new residue to next buffer */
|
|
|
|
if (*next_buff_cnt) {
|
|
|
|
dev_dbg(dev, " handle residue: next buff %pK skip data %u residue %u\n",
|
|
|
|
next_buff, (update_data_len - *curr_buff_cnt),
|
|
|
|
*next_buff_cnt);
|
|
|
|
cc_copy_sg_portion(dev, next_buff, src,
|
|
|
|
(update_data_len - *curr_buff_cnt),
|
|
|
|
nbytes, CC_SG_TO_BUF);
|
|
|
|
/* change the buffer index for next operation */
|
|
|
|
swap_index = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (*curr_buff_cnt) {
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
|
|
|
|
&sg_data);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2018-01-22 17:27:02 +08:00
|
|
|
/* change the buffer index for next operation */
|
|
|
|
swap_index = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (update_data_len > *curr_buff_cnt) {
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_map_sg(dev, src, (update_data_len - *curr_buff_cnt),
|
|
|
|
DMA_TO_DEVICE, &areq_ctx->in_nents,
|
|
|
|
LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy,
|
|
|
|
&mapped_nents);
|
|
|
|
if (rc)
|
2018-01-22 17:27:02 +08:00
|
|
|
goto unmap_curr_buff;
|
|
|
|
if (mapped_nents == 1 &&
|
|
|
|
areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
|
|
|
|
/* only one entry in the SG and no previous data */
|
|
|
|
memcpy(areq_ctx->buff_sg, src,
|
|
|
|
sizeof(struct scatterlist));
|
|
|
|
areq_ctx->buff_sg->length = update_data_len;
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
|
|
|
|
areq_ctx->curr_sg = areq_ctx->buff_sg;
|
|
|
|
} else {
|
|
|
|
areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
|
2020-02-12 02:19:14 +08:00
|
|
|
mlli_params->curr_pool = drvdata->mlli_buffs_pool;
|
2018-01-22 17:27:02 +08:00
|
|
|
/* add the src data to the sg_data */
|
|
|
|
cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src,
|
|
|
|
(update_data_len - *curr_buff_cnt), 0, true,
|
|
|
|
&areq_ctx->mlli_nents);
|
2019-01-15 21:43:11 +08:00
|
|
|
rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
|
|
|
|
if (rc)
|
2018-01-22 17:27:02 +08:00
|
|
|
goto fail_unmap_din;
|
|
|
|
}
|
|
|
|
areq_ctx->buff_index = (areq_ctx->buff_index ^ swap_index);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail_unmap_din:
|
|
|
|
dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
unmap_curr_buff:
|
|
|
|
if (*curr_buff_cnt)
|
|
|
|
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
|
|
|
|
|
2019-01-15 21:43:11 +08:00
|
|
|
return rc;
|
2018-01-22 17:27:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void cc_unmap_hash_request(struct device *dev, void *ctx,
|
|
|
|
struct scatterlist *src, bool do_revert)
|
|
|
|
{
|
|
|
|
struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
|
|
|
|
u32 *prev_len = cc_next_buf_cnt(areq_ctx);
|
|
|
|
|
|
|
|
/*In case a pool was set, a table was
|
|
|
|
*allocated and should be released
|
|
|
|
*/
|
|
|
|
if (areq_ctx->mlli_params.curr_pool) {
|
|
|
|
dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n",
|
|
|
|
&areq_ctx->mlli_params.mlli_dma_addr,
|
|
|
|
areq_ctx->mlli_params.mlli_virt_addr);
|
|
|
|
dma_pool_free(areq_ctx->mlli_params.curr_pool,
|
|
|
|
areq_ctx->mlli_params.mlli_virt_addr,
|
|
|
|
areq_ctx->mlli_params.mlli_dma_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (src && areq_ctx->in_nents) {
|
|
|
|
dev_dbg(dev, "Unmapped sg src: virt=%pK dma=%pad len=0x%X\n",
|
|
|
|
sg_virt(src), &sg_dma_address(src), sg_dma_len(src));
|
|
|
|
dma_unmap_sg(dev, src,
|
|
|
|
areq_ctx->in_nents, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (*prev_len) {
|
|
|
|
dev_dbg(dev, "Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n",
|
|
|
|
sg_virt(areq_ctx->buff_sg),
|
|
|
|
&sg_dma_address(areq_ctx->buff_sg),
|
|
|
|
sg_dma_len(areq_ctx->buff_sg));
|
|
|
|
dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
|
|
|
|
if (!do_revert) {
|
|
|
|
/* clean the previous data length for update
|
|
|
|
* operation
|
|
|
|
*/
|
|
|
|
*prev_len = 0;
|
|
|
|
} else {
|
|
|
|
areq_ctx->buff_index ^= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-22 17:27:00 +08:00
|
|
|
int cc_buffer_mgr_init(struct cc_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
struct device *dev = drvdata_to_dev(drvdata);
|
|
|
|
|
2020-02-12 02:19:14 +08:00
|
|
|
drvdata->mlli_buffs_pool =
|
2018-01-22 17:27:00 +08:00
|
|
|
dma_pool_create("dx_single_mlli_tables", dev,
|
|
|
|
MAX_NUM_OF_TOTAL_MLLI_ENTRIES *
|
|
|
|
LLI_ENTRY_BYTE_SIZE,
|
|
|
|
MLLI_TABLE_MIN_ALIGNMENT, 0);
|
|
|
|
|
2020-02-12 02:19:14 +08:00
|
|
|
if (!drvdata->mlli_buffs_pool)
|
|
|
|
return -ENOMEM;
|
2018-01-22 17:27:00 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cc_buffer_mgr_fini(struct cc_drvdata *drvdata)
|
|
|
|
{
|
2020-02-12 02:19:14 +08:00
|
|
|
dma_pool_destroy(drvdata->mlli_buffs_pool);
|
2018-01-22 17:27:00 +08:00
|
|
|
return 0;
|
|
|
|
}
|