mirror of https://gitee.com/openkylin/linux.git
26 lines
849 B
Plaintext
26 lines
849 B
Plaintext
|
Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
|
||
|
|
-------------------------------------------------------------------
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible : Should be "xlnx,zynqmp-qspi-1.0".
|
||
|
|
- reg : Physical base address and size of GQSPI registers map.
|
||
|
|
- interrupts : Property with a value describing the interrupt
|
||
|
|
number.
|
||
|
|
- clock-names : List of input clock names - "ref_clk", "pclk"
|
||
|
|
(See clock bindings for details).
|
||
|
|
- clocks : Clock phandles (see clock bindings for details).
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
- num-cs : Number of chip selects used.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
qspi: spi@ff0f0000 {
|
||
|
|
compatible = "xlnx,zynqmp-qspi-1.0";
|
||
|
|
clock-names = "ref_clk", "pclk";
|
||
|
|
clocks = <&misc_clk &misc_clk>;
|
||
|
|
interrupts = <0 15 4>;
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
num-cs = <1>;
|
||
|
|
reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
|
||
|
|
};
|