mirror of https://gitee.com/openkylin/linux.git
189 lines
7.1 KiB
C
189 lines
7.1 KiB
C
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/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __MACH_MX28_H__
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#define __MACH_MX28_H__
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#include <mach/mxs.h>
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/*
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* OCRAM
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*/
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#define MX28_OCRAM_BASE_ADDR 0x00000000
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#define MX28_OCRAM_SIZE SZ_128K
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/*
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* IO
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*/
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#define MX28_IO_BASE_ADDR 0x80000000
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#define MX28_IO_SIZE SZ_1M
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#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000)
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#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000)
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#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000)
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#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000)
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#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000)
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#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000)
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#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000)
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#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000)
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#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000)
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#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000)
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#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000)
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#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000)
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#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000)
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#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000)
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#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000)
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#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000)
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#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000)
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#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000)
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#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000)
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#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000)
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#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000)
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#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000)
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#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200)
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#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300)
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#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400)
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#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500)
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#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700)
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#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800)
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#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000)
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#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000)
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#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000)
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#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000)
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#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000)
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#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000)
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#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000)
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#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000)
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#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000)
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#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000)
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#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000)
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#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000)
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#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000)
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#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000)
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#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000)
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#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000)
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#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000)
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#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000)
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#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000)
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#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000)
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#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000)
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#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000)
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#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000)
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#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000)
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#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000)
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#define MX28_IO_P2V(x) MXS_IO_P2V(x)
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#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
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/*
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* IRQ
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*/
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#define MX28_INT_BATT_BRNOUT 0
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#define MX28_INT_VDDD_BRNOUT 1
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#define MX28_INT_VDDIO_BRNOUT 2
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#define MX28_INT_VDDA_BRNOUT 3
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#define MX28_INT_VDD5V_DROOP 4
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#define MX28_INT_DCDC4P2_BRNOUT 5
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#define MX28_INT_VDD5V 6
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#define MX28_INT_CAN0 8
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#define MX28_INT_CAN1 9
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#define MX28_INT_LRADC_TOUCH 10
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#define MX28_INT_HSADC 13
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#define MX28_INT_IRADC_THRESH0 14
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#define MX28_INT_IRADC_THRESH1 15
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#define MX28_INT_LRADC_CH0 16
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#define MX28_INT_LRADC_CH1 17
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#define MX28_INT_LRADC_CH2 18
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#define MX28_INT_LRADC_CH3 19
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#define MX28_INT_LRADC_CH4 20
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#define MX28_INT_LRADC_CH5 21
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#define MX28_INT_LRADC_CH6 22
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#define MX28_INT_LRADC_CH7 23
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#define MX28_INT_LRADC_BUTTON0 24
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#define MX28_INT_LRADC_BUTTON1 25
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#define MX28_INT_PERFMON 27
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#define MX28_INT_RTC_1MSEC 28
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#define MX28_INT_RTC_ALARM 29
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#define MX28_INT_COMMS 31
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#define MX28_INT_EMI_ERR 32
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#define MX28_INT_LCDIF 38
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#define MX28_INT_PXP 39
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#define MX28_INT_BCH 41
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#define MX28_INT_GPMI 42
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#define MX28_INT_SPDIF_ERROR 45
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#define MX28_INT_DUART 47
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#define MX28_INT_TIMER0 48
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#define MX28_INT_TIMER1 49
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#define MX28_INT_TIMER2 50
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#define MX28_INT_TIMER3 51
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#define MX28_INT_DCP_VMI 52
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#define MX28_INT_DCP 53
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#define MX28_INT_DCP_SECURE 54
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#define MX28_INT_SAIF1 58
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#define MX28_INT_SAIF0 59
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#define MX28_INT_SPDIF_DMA 66
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#define MX28_INT_I2C0_DMA 68
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#define MX28_INT_I2C1_DMA 69
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#define MX28_INT_AUART0_RX_DMA 70
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#define MX28_INT_AUART0_TX_DMA 71
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#define MX28_INT_AUART1_RX_DMA 72
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#define MX28_INT_AUART1_TX_DMA 73
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#define MX28_INT_AUART2_RX_DMA 74
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#define MX28_INT_AUART2_TX_DMA 75
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#define MX28_INT_AUART3_RX_DMA 76
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#define MX28_INT_AUART3_TX_DMA 77
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#define MX28_INT_AUART4_RX_DMA 78
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#define MX28_INT_AUART4_TX_DMA 79
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#define MX28_INT_SAIF0_DMA 80
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#define MX28_INT_SAIF1_DMA 81
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#define MX28_INT_SSP0_DMA 82
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#define MX28_INT_SSP1_DMA 83
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#define MX28_INT_SSP2_DMA 84
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#define MX28_INT_SSP3_DMA 85
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#define MX28_INT_LCDIF_DMA 86
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#define MX28_INT_HSADC_DMA 87
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#define MX28_INT_GPMI_DMA 88
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#define MX28_INT_DIGCTL_DEBUG_TRAP 89
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#define MX28_INT_USB1 92
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#define MX28_INT_USB0 93
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#define MX28_INT_USB1_WAKEUP 94
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#define MX28_INT_USB0_WAKEUP 95
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#define MX28_INT_SSP0 96
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#define MX28_INT_SSP1 97
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#define MX28_INT_SSP2 98
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#define MX28_INT_SSP3 99
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#define MX28_INT_ENET_SWI 100
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#define MX28_INT_ENET_MAC0 101
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#define MX28_INT_ENET_MAC1 102
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#define MX28_INT_ENET_MAC0_1588 103
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#define MX28_INT_ENET_MAC1_1588 104
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#define MX28_INT_I2C1_ERROR 110
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#define MX28_INT_I2C0_ERROR 111
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#define MX28_INT_AUART0 112
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#define MX28_INT_AUART1 113
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#define MX28_INT_AUART2 114
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#define MX28_INT_AUART3 115
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#define MX28_INT_AUART4 116
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#define MX28_INT_GPIO4 123
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#define MX28_INT_GPIO3 124
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#define MX28_INT_GPIO2 125
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#define MX28_INT_GPIO1 126
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#define MX28_INT_GPIO0 127
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#endif /* __MACH_MX28_H__ */
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