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linux/drivers/clk/mvebu/cp110-system-controller.c

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clk: mvebu: use SPDX-License-Identifier Convert the remaining files to SPDX license description. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-09-12 21:40:17 +08:00
// SPDX-License-Identifier: GPL-2.0
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
/*
* Marvell Armada CP110 System Controller
*
* Copyright (C) 2016 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
*/
/*
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
* CP110 has 6 core clocks:
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
*
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
* - PLL0 (1 Ghz)
* - PPv2 core (1/3 PLL0)
* - x2 Core (1/2 PLL0)
* - Core (1/2 x2 Core)
* - SDIO (2/5 PLL0)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
*
* - NAND clock, which is either:
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
* - Equal to SDIO clock
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
* - 2/5 PLL0
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
*
clk: mvebu: fix spelling mistake "gatable" -> "gateable" There are a few spelling mistakes in comments and a pr_err error message. Fix these. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-16 19:56:16 +08:00
* CP110 has 32 gateable clocks, for the various peripherals in the IP.
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
*/
#define pr_fmt(fmt) "cp110-system-controller: " fmt
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
#include "armada_ap_cp_helper.h"
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
clk: mvebu: make cp110-system-controller explicitly non-modular The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_CP110_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-05 05:12:13 +08:00
#include <linux/init.h>
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define CP110_PM_CLOCK_GATING_REG 0x220
#define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
#define NF_CLOCK_SEL_400_MASK BIT(0)
enum {
CP110_CLK_TYPE_CORE,
CP110_CLK_TYPE_GATABLE,
};
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
#define CP110_MAX_CORE_CLOCKS 6
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_MAX_GATABLE_CLOCKS 32
#define CP110_CLK_NUM \
(CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
#define CP110_CORE_PLL0 0
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_CORE_PPV2 1
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
#define CP110_CORE_X2CORE 2
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_CORE_CORE 3
#define CP110_CORE_NAND 4
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
#define CP110_CORE_SDIO 5
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: fix spelling mistake "gatable" -> "gateable" There are a few spelling mistakes in comments and a pr_err error message. Fix these. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-16 19:56:16 +08:00
/* A number of gateable clocks need special handling */
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_GATE_AUDIO 0
#define CP110_GATE_COMM_UNIT 1
#define CP110_GATE_NAND 2
#define CP110_GATE_PPV2 3
#define CP110_GATE_SDIO 4
clk: mvebu: adjust clock handling for the CP110 system controller This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21 18:26:56 +08:00
#define CP110_GATE_MG 5
#define CP110_GATE_MG_CORE 6
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_GATE_XOR1 7
#define CP110_GATE_XOR0 8
clk: mvebu: adjust clock handling for the CP110 system controller This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21 18:26:56 +08:00
#define CP110_GATE_GOP_DP 9
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_GATE_PCIE_X1_0 11
#define CP110_GATE_PCIE_X1_1 12
#define CP110_GATE_PCIE_X4 13
#define CP110_GATE_PCIE_XOR 14
#define CP110_GATE_SATA 15
#define CP110_GATE_SATA_USB 16
#define CP110_GATE_MAIN 17
clk: mvebu: adjust clock handling for the CP110 system controller This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21 18:26:56 +08:00
#define CP110_GATE_SDMMC_GOP 18
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
#define CP110_GATE_SLOW_IO 21
#define CP110_GATE_USB3H0 22
#define CP110_GATE_USB3H1 23
#define CP110_GATE_USB3DEV 24
#define CP110_GATE_EIP150 25
#define CP110_GATE_EIP197 26
clk: mvebu: cp110: Minor cleanups Mark an array of strings static const and remove the dereference of a function pointer when assigning to the platform driver probe struct member. drivers/clk/mvebu/cp110-system-controller.c:89:12: warning: symbol 'gate_base_names' was not declared. Should it be static? drivers/clk/mvebu/cp110-system-controller.c:447:18: error: cannot dereference this type Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20 08:11:47 +08:00
static const char * const gate_base_names[] = {
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
[CP110_GATE_AUDIO] = "audio",
[CP110_GATE_COMM_UNIT] = "communit",
[CP110_GATE_NAND] = "nand",
[CP110_GATE_PPV2] = "ppv2",
[CP110_GATE_SDIO] = "sdio",
[CP110_GATE_MG] = "mg-domain",
[CP110_GATE_MG_CORE] = "mg-core",
[CP110_GATE_XOR1] = "xor1",
[CP110_GATE_XOR0] = "xor0",
[CP110_GATE_GOP_DP] = "gop-dp",
[CP110_GATE_PCIE_X1_0] = "pcie_x10",
[CP110_GATE_PCIE_X1_1] = "pcie_x11",
[CP110_GATE_PCIE_X4] = "pcie_x4",
[CP110_GATE_PCIE_XOR] = "pcie-xor",
[CP110_GATE_SATA] = "sata",
[CP110_GATE_SATA_USB] = "sata-usb",
[CP110_GATE_MAIN] = "main",
[CP110_GATE_SDMMC_GOP] = "sd-mmc-gop",
[CP110_GATE_SLOW_IO] = "slow-io",
[CP110_GATE_USB3H0] = "usb3h0",
[CP110_GATE_USB3H1] = "usb3h1",
[CP110_GATE_USB3DEV] = "usb3dev",
[CP110_GATE_EIP150] = "eip150",
[CP110_GATE_EIP197] = "eip197"
};
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
struct cp110_gate_clk {
struct clk_hw hw;
struct regmap *regmap;
u8 bit_idx;
};
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
#define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
static int cp110_gate_enable(struct clk_hw *hw)
{
struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
BIT(gate->bit_idx), BIT(gate->bit_idx));
return 0;
}
static void cp110_gate_disable(struct clk_hw *hw)
{
struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
BIT(gate->bit_idx), 0);
}
static int cp110_gate_is_enabled(struct clk_hw *hw)
{
struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
u32 val;
regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
return val & BIT(gate->bit_idx);
}
static const struct clk_ops cp110_gate_ops = {
.enable = cp110_gate_enable,
.disable = cp110_gate_disable,
.is_enabled = cp110_gate_is_enabled,
};
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
static struct clk_hw *cp110_register_gate(const char *name,
const char *parent_name,
struct regmap *regmap, u8 bit_idx)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
{
struct cp110_gate_clk *gate;
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
struct clk_hw *hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
struct clk_init_data init;
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
int ret;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
clk: mvebu: fix setting unwanted flags in CP110 gate clock Armada CP110 system controller comprises its own routine responsble for registering gate clocks. Among others 'flags' field in struct clk_init_data was not set, using a random values, which may cause an unpredicted behavior. This patch fixes the problem by resetting all fields of clk_init_data before assigning values for all gated clocks of Armada 7k/8k SoCs family. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21 17:05:57 +08:00
memset(&init, 0, sizeof(init));
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
init.name = name;
init.ops = &cp110_gate_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
gate->regmap = regmap;
gate->bit_idx = bit_idx;
gate->hw.init = &init;
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
hw = &gate->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
kfree(gate);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
hw = ERR_PTR(ret);
}
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
return hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
static void cp110_unregister_gate(struct clk_hw *hw)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
{
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
clk_hw_unregister(hw);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
kfree(to_cp110_gate_clk(hw));
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
void *data)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
{
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
struct clk_hw_onecell_data *clk_data = data;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
unsigned int type = clkspec->args[0];
unsigned int idx = clkspec->args[1];
if (type == CP110_CLK_TYPE_CORE) {
clk: mvebu: Off by one bugs in cp110_of_clk_get() These > comparisons should be >= to prevent reading beyond the end of of the clk_data->hws[] buffer. The clk_data->hws[] array is allocated in cp110_syscon_common_probe() when we do: cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) + sizeof(struct clk_hw *) * CP110_CLK_NUM, GFP_KERNEL); As you can see, it has CP110_CLK_NUM elements which is equivalent to CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system controller") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 22:50:55 +08:00
if (idx >= CP110_MAX_CORE_CLOCKS)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
return ERR_PTR(-EINVAL);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
return clk_data->hws[idx];
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
} else if (type == CP110_CLK_TYPE_GATABLE) {
clk: mvebu: Off by one bugs in cp110_of_clk_get() These > comparisons should be >= to prevent reading beyond the end of of the clk_data->hws[] buffer. The clk_data->hws[] array is allocated in cp110_syscon_common_probe() when we do: cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) + sizeof(struct clk_hw *) * CP110_CLK_NUM, GFP_KERNEL); As you can see, it has CP110_CLK_NUM elements which is equivalent to CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system controller") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 22:50:55 +08:00
if (idx >= CP110_MAX_GATABLE_CLOCKS)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
return ERR_PTR(-EINVAL);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
return ERR_PTR(-EINVAL);
}
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
static int cp110_syscon_common_probe(struct platform_device *pdev,
struct device_node *syscon_node)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
{
struct regmap *regmap;
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name,
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
*sdio_name;
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
struct clk_hw_onecell_data *cp110_clk_data;
struct clk_hw *hw, **cp110_clks;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
u32 nand_clk_ctrl;
int i, ret;
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
char *gate_name[ARRAY_SIZE(gate_base_names)];
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
regmap = syscon_node_to_regmap(syscon_node);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
&nand_clk_ctrl);
if (ret)
return ret;
drivers/clk: convert VL struct to struct_size There are a few manually-calculated variable-length struct allocations left, this converts them to use struct_size. Found with the following git grep command git grep -A1 'kzalloc.*sizeof[^_].*+' Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> [sboyd@kernel.org: Add grep command] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-28 02:51:10 +08:00
cp110_clk_data = devm_kzalloc(dev, struct_size(cp110_clk_data, hws,
CP110_CLK_NUM),
clk: mvebu: dynamically allocate resources in Armada CP110 system controller Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21 17:05:58 +08:00
GFP_KERNEL);
if (!cp110_clk_data)
return -ENOMEM;
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
cp110_clks = cp110_clk_data->hws;
cp110_clk_data->num = CP110_CLK_NUM;
clk: mvebu: dynamically allocate resources in Armada CP110 system controller Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21 17:05:58 +08:00
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* Register the PLL0 which is the root of the hw tree */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
1000 * 1000 * 1000);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
goto fail_pll0;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
cp110_clks[CP110_CORE_PLL0] = hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* PPv2 is PLL0/3 */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
goto fail_ppv2;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
cp110_clks[CP110_CORE_PPV2] = hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* X2CORE clock is PLL0/2 */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
0, 1, 2);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
goto fail_eip;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
cp110_clks[CP110_CORE_X2CORE] = hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* Core clock is X2CORE/2 */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
core_name = ap_cp_unique_name(dev, syscon_node, "core");
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
0, 1, 2);
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
goto fail_core;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
cp110_clks[CP110_CORE_CORE] = hw;
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* NAND can be either PLL0/2.5 or core clock */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
hw = clk_hw_register_fixed_factor(NULL, nand_name,
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
pll0_name, 0, 2, 5);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
else
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
hw = clk_hw_register_fixed_factor(NULL, nand_name,
core_name, 0, 1, 1);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
goto fail_nand;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
cp110_clks[CP110_CORE_NAND] = hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
/* SDIO clock is PLL0/2.5 */
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
hw = clk_hw_register_fixed_factor(NULL, sdio_name,
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
pll0_name, 0, 2, 5);
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto fail_sdio;
}
cp110_clks[CP110_CORE_SDIO] = hw;
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
/* create the unique name for all the gate clocks */
for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
clk: mvebu: add helper file for Armada AP and CP clocks Clock drivers for Armada AP and Armada CP use the same function to generate unique clock name. A third drivers is coming with the same need, so it's time to move this function in a common file. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-10 21:43:42 +08:00
gate_name[i] = ap_cp_unique_name(dev, syscon_node,
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
gate_base_names[i]);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
const char *parent;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
if (gate_name[i] == NULL)
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
continue;
switch (i) {
case CP110_GATE_NAND:
parent = nand_name;
break;
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
case CP110_GATE_MG:
case CP110_GATE_GOP_DP:
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
case CP110_GATE_PPV2:
parent = ppv2_name;
break;
case CP110_GATE_SDIO:
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
parent = sdio_name;
break;
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
case CP110_GATE_MAIN:
case CP110_GATE_PCIE_XOR:
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
case CP110_GATE_PCIE_X4:
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
case CP110_GATE_EIP150:
case CP110_GATE_EIP197:
parent = x2core_name;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
break;
default:
parent = core_name;
break;
}
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:11:09 +08:00
hw = cp110_register_gate(gate_name[i], parent, regmap, i);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
goto fail_gate;
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
if (ret)
goto fail_clk_add;
clk: mvebu: dynamically allocate resources in Armada CP110 system controller Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21 17:05:58 +08:00
platform_set_drvdata(pdev, cp110_clks);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
return 0;
fail_clk_add:
fail_gate:
for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
if (hw)
cp110_unregister_gate(hw);
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
}
clk: mvebu: cp110: add sdio clock to cp-110 system controller This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-31 21:19:15 +08:00
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
fail_sdio:
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
fail_nand:
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
fail_core:
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
fail_eip:
clk: mvebu: migrate CP110 system controller to clk_hw API and registration Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-25 15:47:53 +08:00
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
clk: mvebu: cp110: make failure labels more meaningful In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-04-07 21:47:08 +08:00
fail_ppv2:
clk: mvebu: cp110: Fix clock tree representation Thanks to new documentation, we have a better view of the clock tree. There were few mistakes in the first version of this driver, the main one being the parental link between the clocks. Actually the tree is more flat that we though. Most of the IP blocks require two clocks: one for the IP itself and one for accessing the registers, and unlike what we wrote there is no link between these two clocks. The other mistakes were about the name of the clocks: the root clock is not the Audio PLL but the PLL0, and what we called the EIP clock is named the x2 Core clock and is used by other IP block than the EIP ones. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-02-28 22:07:51 +08:00
clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]);
fail_pll0:
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
return ret;
}
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev)
{
dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
dev_warn(&pdev->dev, FW_WARN
"This binding won't be supported in future kernels\n");
return cp110_syscon_common_probe(pdev, pdev->dev.of_node);
}
static int cp110_clk_probe(struct platform_device *pdev)
{
return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent);
}
static const struct of_device_id cp110_syscon_legacy_of_match[] = {
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
{ .compatible = "marvell,cp110-system-controller0", },
{ }
};
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
static struct platform_driver cp110_syscon_legacy_driver = {
clk: mvebu: cp110: Minor cleanups Mark an array of strings static const and remove the dereference of a function pointer when assigning to the platform driver probe struct member. drivers/clk/mvebu/cp110-system-controller.c:89:12: warning: symbol 'gate_base_names' was not declared. Should it be static? drivers/clk/mvebu/cp110-system-controller.c:447:18: error: cannot dereference this type Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20 08:11:47 +08:00
.probe = cp110_syscon_legacy_clk_probe,
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
.driver = {
.name = "marvell-cp110-system-controller0",
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
.of_match_table = cp110_syscon_legacy_of_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver(cp110_syscon_legacy_driver);
static const struct of_device_id cp110_clock_of_match[] = {
{ .compatible = "marvell,cp110-clock", },
{ }
};
static struct platform_driver cp110_clock_driver = {
.probe = cp110_clk_probe,
.driver = {
.name = "marvell-cp110-clock",
.of_match_table = cp110_clock_of_match,
clk: mvebu: make cp110-system-controller explicitly non-modular The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_CP110_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-05 05:12:13 +08:00
.suppress_bind_attrs = true,
clk: mvebu: new driver for Armada CP110 system controller The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-14 23:33:33 +08:00
},
};
clk: mvebu: cp110: introduce a new binding The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-05-30 23:46:06 +08:00
builtin_platform_driver(cp110_clock_driver);