License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2016-03-08 18:49:57 +08:00
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/*
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* Page table allocation functions
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*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#include <linux/sysctl.h>
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2017-06-13 20:46:18 +08:00
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#include <linux/slab.h>
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#include <linux/mm.h>
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2016-03-08 18:49:57 +08:00
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#include <asm/gmap.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_PGSTE
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int page_table_allocate_pgste = 0;
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EXPORT_SYMBOL(page_table_allocate_pgste);
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static struct ctl_table page_table_sysctl[] = {
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{
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.procname = "allocate_pgste",
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.data = &page_table_allocate_pgste,
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.maxlen = sizeof(int),
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.mode = S_IRUGO | S_IWUSR,
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2018-06-24 18:17:43 +08:00
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.proc_handler = proc_dointvec_minmax,
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2019-06-26 06:00:42 +08:00
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.extra1 = SYSCTL_ZERO,
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.extra2 = SYSCTL_ONE,
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2016-03-08 18:49:57 +08:00
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},
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{ }
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};
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static struct ctl_table page_table_sysctl_dir[] = {
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{
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.procname = "vm",
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.maxlen = 0,
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.mode = 0555,
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.child = page_table_sysctl,
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},
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{ }
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};
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static int __init page_table_register_sysctl(void)
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{
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return register_sysctl_table(page_table_sysctl_dir) ? 0 : -ENOMEM;
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}
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__initcall(page_table_register_sysctl);
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#endif /* CONFIG_PGSTE */
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unsigned long *crst_table_alloc(struct mm_struct *mm)
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{
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struct page *page = alloc_pages(GFP_KERNEL, 2);
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if (!page)
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return NULL;
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2016-06-14 18:56:01 +08:00
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arch_set_page_dat(page, 2);
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2016-03-08 18:49:57 +08:00
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return (unsigned long *) page_to_phys(page);
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}
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void crst_table_free(struct mm_struct *mm, unsigned long *table)
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{
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free_pages((unsigned long) table, 2);
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}
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static void __crst_table_upgrade(void *arg)
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{
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struct mm_struct *mm = arg;
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s390: remove all code using the access register mode
The vdso code for the getcpu() and the clock_gettime() call use the access
register mode to access the per-CPU vdso data page with the current code.
An alternative to the complicated AR mode is to use the secondary space
mode. This makes the vdso faster and quite a bit simpler. The downside is
that the uaccess code has to be changed quite a bit.
Which instructions are used depends on the machine and what kind of uaccess
operation is requested. The instruction dictates which ASCE value needs
to be loaded into %cr1 and %cr7.
The different cases:
* User copy with MVCOS for z10 and newer machines
The MVCOS instruction can copy between the primary space (aka user) and
the home space (aka kernel) directly. For set_fs(KERNEL_DS) the kernel
ASCE is loaded into %cr1. For set_fs(USER_DS) the user space is already
loaded in %cr1.
* User copy with MVCP/MVCS for older machines
To be able to execute the MVCP/MVCS instructions the kernel needs to
switch to primary mode. The control register %cr1 has to be set to the
kernel ASCE and %cr7 to either the kernel ASCE or the user ASCE dependent
on set_fs(KERNEL_DS) vs set_fs(USER_DS).
* Data access in the user address space for strnlen / futex
To use "normal" instruction with data from the user address space the
secondary space mode is used. The kernel needs to switch to primary mode,
%cr1 has to contain the kernel ASCE and %cr7 either the user ASCE or the
kernel ASCE, dependent on set_fs.
To load a new value into %cr1 or %cr7 is an expensive operation, the kernel
tries to be lazy about it. E.g. for multiple user copies in a row with
MVCP/MVCS the replacement of the vdso ASCE in %cr7 with the user ASCE is
done only once. On return to user space a CPU bit is checked that loads the
vdso ASCE again.
To enable and disable the data access via the secondary space two new
functions are added, enable_sacf_uaccess and disable_sacf_uaccess. The fact
that a context is in secondary space uaccess mode is stored in the
mm_segment_t value for the task. The code of an interrupt may use set_fs
as long as it returns to the previous state it got with get_fs with another
call to set_fs. The code in finish_arch_post_lock_switch simply has to do a
set_fs with the current mm_segment_t value for the task.
For CPUs with MVCOS:
CPU running in | %cr1 ASCE | %cr7 ASCE |
--------------------------------------|-----------|-----------|
user space | user | vdso |
kernel, USER_DS, normal-mode | user | vdso |
kernel, USER_DS, normal-mode, lazy | user | user |
kernel, USER_DS, sacf-mode | kernel | user |
kernel, KERNEL_DS, normal-mode | kernel | vdso |
kernel, KERNEL_DS, normal-mode, lazy | kernel | kernel |
kernel, KERNEL_DS, sacf-mode | kernel | kernel |
For CPUs without MVCOS:
CPU running in | %cr1 ASCE | %cr7 ASCE |
--------------------------------------|-----------|-----------|
user space | user | vdso |
kernel, USER_DS, normal-mode | user | vdso |
kernel, USER_DS, normal-mode lazy | kernel | user |
kernel, USER_DS, sacf-mode | kernel | user |
kernel, KERNEL_DS, normal-mode | kernel | vdso |
kernel, KERNEL_DS, normal-mode, lazy | kernel | kernel |
kernel, KERNEL_DS, sacf-mode | kernel | kernel |
The lines with "lazy" refer to the state after a copy via the secondary
space with a delayed reload of %cr1 and %cr7.
There are three hardware address spaces that can cause a DAT exception,
primary, secondary and home space. The exception can be related to
four different fault types: user space fault, vdso fault, kernel fault,
and the gmap faults.
Dependent on the set_fs state and normal vs. sacf mode there are a number
of fault combinations:
1) user address space fault via the primary ASCE
2) gmap address space fault via the primary ASCE
3) kernel address space fault via the primary ASCE for machines with
MVCOS and set_fs(KERNEL_DS)
4) vdso address space faults via the secondary ASCE with an invalid
address while running in secondary space in problem state
5) user address space fault via the secondary ASCE for user-copy
based on the secondary space mode, e.g. futex_ops or strnlen_user
6) kernel address space fault via the secondary ASCE for user-copy
with secondary space mode with set_fs(KERNEL_DS)
7) kernel address space fault via the primary ASCE for user-copy
with secondary space mode with set_fs(USER_DS) on machines without
MVCOS.
8) kernel address space fault via the home space ASCE
Replace user_space_fault() with a new function get_fault_type() that
can distinguish all four different fault types.
With these changes the futex atomic ops from the kernel and the
strnlen_user will get a little bit slower, as well as the old style
uaccess with MVCP/MVCS. All user accesses based on MVCOS will be as
fast as before. On the positive side, the user space vdso code is a
lot faster and Linux ceases to use the complicated AR mode.
Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2017-08-22 18:08:22 +08:00
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if (current->active_mm == mm)
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2016-03-08 18:49:57 +08:00
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set_user_asce(mm);
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__tlb_flush_local();
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}
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2017-04-25 00:19:10 +08:00
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int crst_table_upgrade(struct mm_struct *mm, unsigned long end)
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2016-03-08 18:49:57 +08:00
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{
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unsigned long *table, *pgd;
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2017-04-25 00:19:10 +08:00
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int rc, notify;
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2016-03-08 18:49:57 +08:00
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2017-04-25 00:19:10 +08:00
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/* upgrade should only happen from 3 to 4, 3 to 5, or 4 to 5 levels */
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2017-08-31 19:18:22 +08:00
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VM_BUG_ON(mm->context.asce_limit < _REGION2_SIZE);
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2017-04-25 00:19:10 +08:00
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rc = 0;
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notify = 0;
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while (mm->context.asce_limit < end) {
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table = crst_table_alloc(mm);
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if (!table) {
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rc = -ENOMEM;
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break;
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}
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spin_lock_bh(&mm->page_table_lock);
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pgd = (unsigned long *) mm->pgd;
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2017-07-05 13:37:27 +08:00
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if (mm->context.asce_limit == _REGION2_SIZE) {
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2017-04-25 00:19:10 +08:00
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crst_table_init(table, _REGION2_ENTRY_EMPTY);
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p4d_populate(mm, (p4d_t *) table, (pud_t *) pgd);
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mm->pgd = (pgd_t *) table;
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2017-07-05 13:37:27 +08:00
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mm->context.asce_limit = _REGION1_SIZE;
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2017-04-25 00:19:10 +08:00
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mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
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_ASCE_USER_BITS | _ASCE_TYPE_REGION2;
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2018-10-15 17:09:16 +08:00
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mm_inc_nr_puds(mm);
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2017-04-25 00:19:10 +08:00
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} else {
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crst_table_init(table, _REGION1_ENTRY_EMPTY);
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pgd_populate(mm, (pgd_t *) table, (p4d_t *) pgd);
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mm->pgd = (pgd_t *) table;
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mm->context.asce_limit = -PAGE_SIZE;
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mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
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_ASCE_USER_BITS | _ASCE_TYPE_REGION1;
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}
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notify = 1;
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spin_unlock_bh(&mm->page_table_lock);
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}
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if (notify)
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on_each_cpu(__crst_table_upgrade, mm, 0);
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return rc;
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2016-03-08 18:49:57 +08:00
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}
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s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
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void crst_table_downgrade(struct mm_struct *mm)
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2016-03-08 18:49:57 +08:00
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{
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pgd_t *pgd;
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s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
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/* downgrade should only happen from 3 to 2 levels (compat only) */
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2017-08-31 19:18:22 +08:00
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VM_BUG_ON(mm->context.asce_limit != _REGION2_SIZE);
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s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
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2016-03-08 18:49:57 +08:00
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if (current->active_mm == mm) {
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clear_user_asce();
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__tlb_flush_mm(mm);
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}
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s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
|
|
|
|
|
|
|
pgd = mm->pgd;
|
2018-11-27 21:04:04 +08:00
|
|
|
mm_dec_nr_pmds(mm);
|
s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
|
|
|
mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN);
|
2017-07-05 13:37:27 +08:00
|
|
|
mm->context.asce_limit = _REGION3_SIZE;
|
s390/mm: fix asce_bits handling with dynamic pagetable levels
There is a race with multi-threaded applications between context switch and
pagetable upgrade. In switch_mm() a new user_asce is built from mm->pgd and
mm->context.asce_bits, w/o holding any locks. A concurrent mmap with a
pagetable upgrade on another thread in crst_table_upgrade() could already
have set new asce_bits, but not yet the new mm->pgd. This would result in a
corrupt user_asce in switch_mm(), and eventually in a kernel panic from a
translation exception.
Fix this by storing the complete asce instead of just the asce_bits, which
can then be read atomically from switch_mm(), so that it either sees the
old value or the new value, but no mixture. Both cases are OK. Having the
old value would result in a page fault on access to the higher level memory,
but the fault handler would see the new mm->pgd, if it was a valid access
after the mmap on the other thread has completed. So as worst-case scenario
we would have a page fault loop for the racing thread until the next time
slice.
Also remove dead code and simplify the upgrade/downgrade path, there are no
upgrades from 2 levels, and only downgrades from 3 levels for compat tasks.
There are also no concurrent upgrades, because the mmap_sem is held with
down_write() in do_mmap, so the flush and table checks during upgrade can
be removed.
Reported-by: Michael Munday <munday@ca.ibm.com>
Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-04-15 22:38:40 +08:00
|
|
|
mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
|
|
|
|
_ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
|
|
|
|
crst_table_free(mm, (unsigned long *) pgd);
|
|
|
|
|
2016-03-08 18:49:57 +08:00
|
|
|
if (current->active_mm == mm)
|
|
|
|
set_user_asce(mm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int atomic_xor_bits(atomic_t *v, unsigned int bits)
|
|
|
|
{
|
|
|
|
unsigned int old, new;
|
|
|
|
|
|
|
|
do {
|
|
|
|
old = atomic_read(v);
|
|
|
|
new = old ^ bits;
|
|
|
|
} while (atomic_cmpxchg(v, old, new) != old);
|
|
|
|
return new;
|
|
|
|
}
|
|
|
|
|
2016-03-08 19:12:18 +08:00
|
|
|
#ifdef CONFIG_PGSTE
|
|
|
|
|
|
|
|
struct page *page_table_alloc_pgste(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
struct page *page;
|
2017-10-05 01:27:07 +08:00
|
|
|
u64 *table;
|
2016-03-08 19:12:18 +08:00
|
|
|
|
2017-03-07 23:48:40 +08:00
|
|
|
page = alloc_page(GFP_KERNEL);
|
2016-03-08 19:12:18 +08:00
|
|
|
if (page) {
|
2017-10-05 01:27:07 +08:00
|
|
|
table = (u64 *)page_to_phys(page);
|
|
|
|
memset64(table, _PAGE_INVALID, PTRS_PER_PTE);
|
|
|
|
memset64(table + PTRS_PER_PTE, 0, PTRS_PER_PTE);
|
2016-03-08 19:12:18 +08:00
|
|
|
}
|
|
|
|
return page;
|
|
|
|
}
|
|
|
|
|
|
|
|
void page_table_free_pgste(struct page *page)
|
|
|
|
{
|
|
|
|
__free_page(page);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_PGSTE */
|
|
|
|
|
2016-03-08 18:49:57 +08:00
|
|
|
/*
|
|
|
|
* page table entry allocation/free routines.
|
|
|
|
*/
|
|
|
|
unsigned long *page_table_alloc(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
unsigned long *table;
|
|
|
|
struct page *page;
|
|
|
|
unsigned int mask, bit;
|
|
|
|
|
|
|
|
/* Try to get a fragment of a 4K page as a 2K page table */
|
|
|
|
if (!mm_alloc_pgste(mm)) {
|
|
|
|
table = NULL;
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_lock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
if (!list_empty(&mm->context.pgtable_list)) {
|
|
|
|
page = list_first_entry(&mm->context.pgtable_list,
|
|
|
|
struct page, lru);
|
2018-06-08 08:08:15 +08:00
|
|
|
mask = atomic_read(&page->_refcount) >> 24;
|
2016-03-08 18:49:57 +08:00
|
|
|
mask = (mask | (mask >> 4)) & 3;
|
|
|
|
if (mask != 3) {
|
|
|
|
table = (unsigned long *) page_to_phys(page);
|
|
|
|
bit = mask & 1; /* =1 -> second 2K */
|
|
|
|
if (bit)
|
|
|
|
table += PTRS_PER_PTE;
|
2018-06-08 08:08:15 +08:00
|
|
|
atomic_xor_bits(&page->_refcount,
|
|
|
|
1U << (bit + 24));
|
2016-03-08 18:49:57 +08:00
|
|
|
list_del(&page->lru);
|
|
|
|
}
|
|
|
|
}
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_unlock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
if (table)
|
|
|
|
return table;
|
|
|
|
}
|
|
|
|
/* Allocate a fresh page */
|
2016-06-25 05:49:17 +08:00
|
|
|
page = alloc_page(GFP_KERNEL);
|
2016-03-08 18:49:57 +08:00
|
|
|
if (!page)
|
|
|
|
return NULL;
|
2019-09-26 07:49:46 +08:00
|
|
|
if (!pgtable_pte_page_ctor(page)) {
|
2016-03-08 18:49:57 +08:00
|
|
|
__free_page(page);
|
|
|
|
return NULL;
|
|
|
|
}
|
2016-06-14 18:56:01 +08:00
|
|
|
arch_set_page_dat(page, 0);
|
2016-03-08 18:49:57 +08:00
|
|
|
/* Initialize page table */
|
|
|
|
table = (unsigned long *) page_to_phys(page);
|
|
|
|
if (mm_alloc_pgste(mm)) {
|
|
|
|
/* Return 4K page table with PGSTEs */
|
2018-06-08 08:08:15 +08:00
|
|
|
atomic_xor_bits(&page->_refcount, 3 << 24);
|
2017-10-05 01:27:07 +08:00
|
|
|
memset64((u64 *)table, _PAGE_INVALID, PTRS_PER_PTE);
|
|
|
|
memset64((u64 *)table + PTRS_PER_PTE, 0, PTRS_PER_PTE);
|
2016-03-08 18:49:57 +08:00
|
|
|
} else {
|
|
|
|
/* Return the first 2K fragment of the page */
|
2018-06-08 08:08:15 +08:00
|
|
|
atomic_xor_bits(&page->_refcount, 1 << 24);
|
2017-10-05 01:27:07 +08:00
|
|
|
memset64((u64 *)table, _PAGE_INVALID, 2 * PTRS_PER_PTE);
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_lock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
list_add(&page->lru, &mm->context.pgtable_list);
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_unlock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
}
|
|
|
|
return table;
|
|
|
|
}
|
|
|
|
|
|
|
|
void page_table_free(struct mm_struct *mm, unsigned long *table)
|
|
|
|
{
|
|
|
|
struct page *page;
|
|
|
|
unsigned int bit, mask;
|
|
|
|
|
|
|
|
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
|
|
|
|
if (!mm_alloc_pgste(mm)) {
|
|
|
|
/* Free 2K page table fragment of a 4K page */
|
|
|
|
bit = (__pa(table) & ~PAGE_MASK)/(PTRS_PER_PTE*sizeof(pte_t));
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_lock_bh(&mm->context.lock);
|
2018-06-08 08:08:15 +08:00
|
|
|
mask = atomic_xor_bits(&page->_refcount, 1U << (bit + 24));
|
|
|
|
mask >>= 24;
|
2016-03-08 18:49:57 +08:00
|
|
|
if (mask & 3)
|
|
|
|
list_add(&page->lru, &mm->context.pgtable_list);
|
|
|
|
else
|
|
|
|
list_del(&page->lru);
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_unlock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
if (mask != 0)
|
|
|
|
return;
|
2018-06-30 01:54:01 +08:00
|
|
|
} else {
|
|
|
|
atomic_xor_bits(&page->_refcount, 3U << 24);
|
2016-03-08 18:49:57 +08:00
|
|
|
}
|
|
|
|
|
2019-09-26 07:49:46 +08:00
|
|
|
pgtable_pte_page_dtor(page);
|
2016-03-08 18:49:57 +08:00
|
|
|
__free_page(page);
|
|
|
|
}
|
|
|
|
|
|
|
|
void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table,
|
|
|
|
unsigned long vmaddr)
|
|
|
|
{
|
|
|
|
struct mm_struct *mm;
|
|
|
|
struct page *page;
|
|
|
|
unsigned int bit, mask;
|
|
|
|
|
|
|
|
mm = tlb->mm;
|
|
|
|
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
|
|
|
|
if (mm_alloc_pgste(mm)) {
|
|
|
|
gmap_unlink(mm, table, vmaddr);
|
|
|
|
table = (unsigned long *) (__pa(table) | 3);
|
|
|
|
tlb_remove_table(tlb, table);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
bit = (__pa(table) & ~PAGE_MASK) / (PTRS_PER_PTE*sizeof(pte_t));
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_lock_bh(&mm->context.lock);
|
2018-06-08 08:08:15 +08:00
|
|
|
mask = atomic_xor_bits(&page->_refcount, 0x11U << (bit + 24));
|
|
|
|
mask >>= 24;
|
2016-03-08 18:49:57 +08:00
|
|
|
if (mask & 3)
|
|
|
|
list_add_tail(&page->lru, &mm->context.pgtable_list);
|
|
|
|
else
|
|
|
|
list_del(&page->lru);
|
2017-08-18 00:17:49 +08:00
|
|
|
spin_unlock_bh(&mm->context.lock);
|
2016-03-08 18:49:57 +08:00
|
|
|
table = (unsigned long *) (__pa(table) | (1U << bit));
|
|
|
|
tlb_remove_table(tlb, table);
|
|
|
|
}
|
|
|
|
|
2018-09-18 20:51:51 +08:00
|
|
|
void __tlb_remove_table(void *_table)
|
2016-03-08 18:49:57 +08:00
|
|
|
{
|
|
|
|
unsigned int mask = (unsigned long) _table & 3;
|
|
|
|
void *table = (void *)((unsigned long) _table ^ mask);
|
|
|
|
struct page *page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
|
|
|
|
|
|
|
|
switch (mask) {
|
2017-04-25 00:19:10 +08:00
|
|
|
case 0: /* pmd, pud, or p4d */
|
2016-03-08 18:49:57 +08:00
|
|
|
free_pages((unsigned long) table, 2);
|
|
|
|
break;
|
|
|
|
case 1: /* lower 2K of a 4K page table */
|
|
|
|
case 2: /* higher 2K of a 4K page table */
|
2018-06-08 08:08:15 +08:00
|
|
|
mask = atomic_xor_bits(&page->_refcount, mask << (4 + 24));
|
|
|
|
mask >>= 24;
|
|
|
|
if (mask != 0)
|
2016-03-08 18:49:57 +08:00
|
|
|
break;
|
|
|
|
/* fallthrough */
|
|
|
|
case 3: /* 4K page table with pgstes */
|
2018-06-30 01:54:01 +08:00
|
|
|
if (mask & 3)
|
|
|
|
atomic_xor_bits(&page->_refcount, 3 << 24);
|
2019-09-26 07:49:46 +08:00
|
|
|
pgtable_pte_page_dtor(page);
|
2016-03-08 18:49:57 +08:00
|
|
|
__free_page(page);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-06-13 20:46:18 +08:00
|
|
|
/*
|
|
|
|
* Base infrastructure required to generate basic asces, region, segment,
|
|
|
|
* and page tables that do not make use of enhanced features like EDAT1.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct kmem_cache *base_pgt_cache;
|
|
|
|
|
|
|
|
static unsigned long base_pgt_alloc(void)
|
|
|
|
{
|
|
|
|
u64 *table;
|
|
|
|
|
|
|
|
table = kmem_cache_alloc(base_pgt_cache, GFP_KERNEL);
|
|
|
|
if (table)
|
|
|
|
memset64(table, _PAGE_INVALID, PTRS_PER_PTE);
|
|
|
|
return (unsigned long) table;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void base_pgt_free(unsigned long table)
|
|
|
|
{
|
|
|
|
kmem_cache_free(base_pgt_cache, (void *) table);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long base_crst_alloc(unsigned long val)
|
|
|
|
{
|
|
|
|
unsigned long table;
|
|
|
|
|
|
|
|
table = __get_free_pages(GFP_KERNEL, CRST_ALLOC_ORDER);
|
|
|
|
if (table)
|
|
|
|
crst_table_init((unsigned long *)table, val);
|
|
|
|
return table;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void base_crst_free(unsigned long table)
|
|
|
|
{
|
|
|
|
free_pages(table, CRST_ALLOC_ORDER);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define BASE_ADDR_END_FUNC(NAME, SIZE) \
|
|
|
|
static inline unsigned long base_##NAME##_addr_end(unsigned long addr, \
|
|
|
|
unsigned long end) \
|
|
|
|
{ \
|
|
|
|
unsigned long next = (addr + (SIZE)) & ~((SIZE) - 1); \
|
|
|
|
\
|
|
|
|
return (next - 1) < (end - 1) ? next : end; \
|
|
|
|
}
|
|
|
|
|
|
|
|
BASE_ADDR_END_FUNC(page, _PAGE_SIZE)
|
|
|
|
BASE_ADDR_END_FUNC(segment, _SEGMENT_SIZE)
|
|
|
|
BASE_ADDR_END_FUNC(region3, _REGION3_SIZE)
|
|
|
|
BASE_ADDR_END_FUNC(region2, _REGION2_SIZE)
|
|
|
|
BASE_ADDR_END_FUNC(region1, _REGION1_SIZE)
|
|
|
|
|
|
|
|
static inline unsigned long base_lra(unsigned long address)
|
|
|
|
{
|
|
|
|
unsigned long real;
|
|
|
|
|
|
|
|
asm volatile(
|
|
|
|
" lra %0,0(%1)\n"
|
|
|
|
: "=d" (real) : "a" (address) : "cc");
|
|
|
|
return real;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_page_walk(unsigned long origin, unsigned long addr,
|
|
|
|
unsigned long end, int alloc)
|
|
|
|
{
|
|
|
|
unsigned long *pte, next;
|
|
|
|
|
|
|
|
if (!alloc)
|
|
|
|
return 0;
|
|
|
|
pte = (unsigned long *) origin;
|
|
|
|
pte += (addr & _PAGE_INDEX) >> _PAGE_SHIFT;
|
|
|
|
do {
|
|
|
|
next = base_page_addr_end(addr, end);
|
|
|
|
*pte = base_lra(addr);
|
|
|
|
} while (pte++, addr = next, addr < end);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_segment_walk(unsigned long origin, unsigned long addr,
|
|
|
|
unsigned long end, int alloc)
|
|
|
|
{
|
|
|
|
unsigned long *ste, next, table;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ste = (unsigned long *) origin;
|
|
|
|
ste += (addr & _SEGMENT_INDEX) >> _SEGMENT_SHIFT;
|
|
|
|
do {
|
|
|
|
next = base_segment_addr_end(addr, end);
|
|
|
|
if (*ste & _SEGMENT_ENTRY_INVALID) {
|
|
|
|
if (!alloc)
|
|
|
|
continue;
|
|
|
|
table = base_pgt_alloc();
|
|
|
|
if (!table)
|
|
|
|
return -ENOMEM;
|
|
|
|
*ste = table | _SEGMENT_ENTRY;
|
|
|
|
}
|
|
|
|
table = *ste & _SEGMENT_ENTRY_ORIGIN;
|
|
|
|
rc = base_page_walk(table, addr, next, alloc);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
if (!alloc)
|
|
|
|
base_pgt_free(table);
|
|
|
|
cond_resched();
|
|
|
|
} while (ste++, addr = next, addr < end);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_region3_walk(unsigned long origin, unsigned long addr,
|
|
|
|
unsigned long end, int alloc)
|
|
|
|
{
|
|
|
|
unsigned long *rtte, next, table;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rtte = (unsigned long *) origin;
|
|
|
|
rtte += (addr & _REGION3_INDEX) >> _REGION3_SHIFT;
|
|
|
|
do {
|
|
|
|
next = base_region3_addr_end(addr, end);
|
|
|
|
if (*rtte & _REGION_ENTRY_INVALID) {
|
|
|
|
if (!alloc)
|
|
|
|
continue;
|
|
|
|
table = base_crst_alloc(_SEGMENT_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return -ENOMEM;
|
|
|
|
*rtte = table | _REGION3_ENTRY;
|
|
|
|
}
|
|
|
|
table = *rtte & _REGION_ENTRY_ORIGIN;
|
|
|
|
rc = base_segment_walk(table, addr, next, alloc);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
if (!alloc)
|
|
|
|
base_crst_free(table);
|
|
|
|
} while (rtte++, addr = next, addr < end);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_region2_walk(unsigned long origin, unsigned long addr,
|
|
|
|
unsigned long end, int alloc)
|
|
|
|
{
|
|
|
|
unsigned long *rste, next, table;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rste = (unsigned long *) origin;
|
|
|
|
rste += (addr & _REGION2_INDEX) >> _REGION2_SHIFT;
|
|
|
|
do {
|
|
|
|
next = base_region2_addr_end(addr, end);
|
|
|
|
if (*rste & _REGION_ENTRY_INVALID) {
|
|
|
|
if (!alloc)
|
|
|
|
continue;
|
|
|
|
table = base_crst_alloc(_REGION3_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return -ENOMEM;
|
|
|
|
*rste = table | _REGION2_ENTRY;
|
|
|
|
}
|
|
|
|
table = *rste & _REGION_ENTRY_ORIGIN;
|
|
|
|
rc = base_region3_walk(table, addr, next, alloc);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
if (!alloc)
|
|
|
|
base_crst_free(table);
|
|
|
|
} while (rste++, addr = next, addr < end);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_region1_walk(unsigned long origin, unsigned long addr,
|
|
|
|
unsigned long end, int alloc)
|
|
|
|
{
|
|
|
|
unsigned long *rfte, next, table;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rfte = (unsigned long *) origin;
|
|
|
|
rfte += (addr & _REGION1_INDEX) >> _REGION1_SHIFT;
|
|
|
|
do {
|
|
|
|
next = base_region1_addr_end(addr, end);
|
|
|
|
if (*rfte & _REGION_ENTRY_INVALID) {
|
|
|
|
if (!alloc)
|
|
|
|
continue;
|
|
|
|
table = base_crst_alloc(_REGION2_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return -ENOMEM;
|
|
|
|
*rfte = table | _REGION1_ENTRY;
|
|
|
|
}
|
|
|
|
table = *rfte & _REGION_ENTRY_ORIGIN;
|
|
|
|
rc = base_region2_walk(table, addr, next, alloc);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
if (!alloc)
|
|
|
|
base_crst_free(table);
|
|
|
|
} while (rfte++, addr = next, addr < end);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* base_asce_free - free asce and tables returned from base_asce_alloc()
|
|
|
|
* @asce: asce to be freed
|
|
|
|
*
|
|
|
|
* Frees all region, segment, and page tables that were allocated with a
|
|
|
|
* corresponding base_asce_alloc() call.
|
|
|
|
*/
|
|
|
|
void base_asce_free(unsigned long asce)
|
|
|
|
{
|
|
|
|
unsigned long table = asce & _ASCE_ORIGIN;
|
|
|
|
|
|
|
|
if (!asce)
|
|
|
|
return;
|
|
|
|
switch (asce & _ASCE_TYPE_MASK) {
|
|
|
|
case _ASCE_TYPE_SEGMENT:
|
|
|
|
base_segment_walk(table, 0, _REGION3_SIZE, 0);
|
|
|
|
break;
|
|
|
|
case _ASCE_TYPE_REGION3:
|
|
|
|
base_region3_walk(table, 0, _REGION2_SIZE, 0);
|
|
|
|
break;
|
|
|
|
case _ASCE_TYPE_REGION2:
|
|
|
|
base_region2_walk(table, 0, _REGION1_SIZE, 0);
|
|
|
|
break;
|
|
|
|
case _ASCE_TYPE_REGION1:
|
|
|
|
base_region1_walk(table, 0, -_PAGE_SIZE, 0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
base_crst_free(table);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int base_pgt_cache_init(void)
|
|
|
|
{
|
|
|
|
static DEFINE_MUTEX(base_pgt_cache_mutex);
|
|
|
|
unsigned long sz = _PAGE_TABLE_SIZE;
|
|
|
|
|
|
|
|
if (base_pgt_cache)
|
|
|
|
return 0;
|
|
|
|
mutex_lock(&base_pgt_cache_mutex);
|
|
|
|
if (!base_pgt_cache)
|
|
|
|
base_pgt_cache = kmem_cache_create("base_pgt", sz, sz, 0, NULL);
|
|
|
|
mutex_unlock(&base_pgt_cache_mutex);
|
|
|
|
return base_pgt_cache ? 0 : -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* base_asce_alloc - create kernel mapping without enhanced DAT features
|
|
|
|
* @addr: virtual start address of kernel mapping
|
|
|
|
* @num_pages: number of consecutive pages
|
|
|
|
*
|
|
|
|
* Generate an asce, including all required region, segment and page tables,
|
|
|
|
* that can be used to access the virtual kernel mapping. The difference is
|
|
|
|
* that the returned asce does not make use of any enhanced DAT features like
|
|
|
|
* e.g. large pages. This is required for some I/O functions that pass an
|
|
|
|
* asce, like e.g. some service call requests.
|
|
|
|
*
|
|
|
|
* Note: the returned asce may NEVER be attached to any cpu. It may only be
|
|
|
|
* used for I/O requests. tlb entries that might result because the
|
|
|
|
* asce was attached to a cpu won't be cleared.
|
|
|
|
*/
|
|
|
|
unsigned long base_asce_alloc(unsigned long addr, unsigned long num_pages)
|
|
|
|
{
|
|
|
|
unsigned long asce, table, end;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (base_pgt_cache_init())
|
|
|
|
return 0;
|
|
|
|
end = addr + num_pages * PAGE_SIZE;
|
|
|
|
if (end <= _REGION3_SIZE) {
|
|
|
|
table = base_crst_alloc(_SEGMENT_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return 0;
|
|
|
|
rc = base_segment_walk(table, addr, end, 1);
|
|
|
|
asce = table | _ASCE_TYPE_SEGMENT | _ASCE_TABLE_LENGTH;
|
|
|
|
} else if (end <= _REGION2_SIZE) {
|
|
|
|
table = base_crst_alloc(_REGION3_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return 0;
|
|
|
|
rc = base_region3_walk(table, addr, end, 1);
|
|
|
|
asce = table | _ASCE_TYPE_REGION3 | _ASCE_TABLE_LENGTH;
|
|
|
|
} else if (end <= _REGION1_SIZE) {
|
|
|
|
table = base_crst_alloc(_REGION2_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return 0;
|
|
|
|
rc = base_region2_walk(table, addr, end, 1);
|
|
|
|
asce = table | _ASCE_TYPE_REGION2 | _ASCE_TABLE_LENGTH;
|
|
|
|
} else {
|
|
|
|
table = base_crst_alloc(_REGION1_ENTRY_EMPTY);
|
|
|
|
if (!table)
|
|
|
|
return 0;
|
|
|
|
rc = base_region1_walk(table, addr, end, 1);
|
|
|
|
asce = table | _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH;
|
|
|
|
}
|
|
|
|
if (rc) {
|
|
|
|
base_asce_free(asce);
|
|
|
|
asce = 0;
|
|
|
|
}
|
|
|
|
return asce;
|
|
|
|
}
|