2013-03-20 01:53:03 +08:00
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/*
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* Device Tree Source for OMAP34xx/OMAP35xx SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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2018-01-12 08:04:03 +08:00
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#include <dt-bindings/bus/ti-sysc.h>
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2015-03-19 07:50:23 +08:00
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#include <dt-bindings/media/omap3-isp.h>
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2013-05-31 20:32:55 +08:00
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#include "omap3.dtsi"
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2013-03-20 01:53:03 +08:00
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/ {
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cpus {
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2017-03-09 16:05:55 +08:00
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cpu: cpu@0 {
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2013-03-20 01:53:03 +08:00
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/* OMAP343x/OMAP35xx variants OPP1-5 */
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operating-points = <
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/* kHz uV */
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125000 975000
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250000 1075000
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500000 1200000
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550000 1270000
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600000 1350000
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>;
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clock-latency = <300000>; /* From legacy driver */
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};
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};
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2014-01-08 06:01:39 +08:00
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2016-08-02 00:46:55 +08:00
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ocp@68000000 {
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2014-01-08 06:01:39 +08:00
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omap3_pmx_core2: pinmux@480025d8 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025d8 0x24>;
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#address-cells = <1>;
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#size-cells = <0>;
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2016-11-07 23:27:49 +08:00
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#pinctrl-cells = <1>;
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2014-01-08 06:01:39 +08:00
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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2015-03-19 07:50:23 +08:00
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isp: isp@480bc000 {
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compatible = "ti,omap3-isp";
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reg = <0x480bc000 0x12fc
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0x480bd800 0x017c>;
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interrupts = <24>;
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iommus = <&mmu_isp>;
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2016-04-16 14:20:28 +08:00
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syscon = <&scm_conf 0x6c>;
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2015-03-19 07:50:23 +08:00
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ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
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#clock-cells = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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2015-12-26 07:32:25 +08:00
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2017-03-09 16:05:55 +08:00
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bandgap: bandgap@48002524 {
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2015-12-26 07:32:25 +08:00
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reg = <0x48002524 0x4>;
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compatible = "ti,omap34xx-bandgap";
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#thermal-sensor-cells = <0>;
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};
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2018-01-12 08:04:03 +08:00
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target-module@480cb000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480cb000 0x001000>;
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smartreflex_core: smartreflex@0 {
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compatible = "ti,omap3-smartreflex-core";
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reg = <0 0x400>;
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interrupts = <19>;
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};
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};
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target-module@480c9000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480c9000 0x001000>;
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-mpu-iva";
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reg = <0 0x400>;
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interrupts = <18>;
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};
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};
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2019-08-26 23:47:08 +08:00
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/*
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* On omap34xx the OCP registers do not seem to be accessible
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* at all unlike on 36xx. Maybe SGX is permanently set to
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* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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* write-only at 0x50000e10. We detect SGX based on the SGX
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* revision register instead of the unreadable OCP revision
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* register. Also note that on early 34xx es1 revision there
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* are also different clocks, but we do not have any dts users
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* for it.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000014 0x4>;
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reg-names = "rev";
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x4000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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2014-01-08 06:01:39 +08:00
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};
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2017-03-09 16:05:55 +08:00
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thermal_zones: thermal-zones {
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#include "omap3-cpu-thermal.dtsi"
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};
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2013-03-20 01:53:03 +08:00
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};
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2013-07-22 17:29:29 +08:00
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2014-05-11 00:37:49 +08:00
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&ssi {
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status = "ok";
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clocks = <&ssi_ssr_fck>,
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<&ssi_sst_fck>,
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<&ssi_ick>;
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clock-names = "ssi_ssr_fck",
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"ssi_sst_fck",
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"ssi_ick";
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};
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2013-07-22 17:29:29 +08:00
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/include/ "omap34xx-omap36xx-clocks.dtsi"
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/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
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2014-01-29 10:44:53 +08:00
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/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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