2018-08-31 00:52:54 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2014-06-03 13:26:02 +08:00
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/*
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2018-08-31 00:52:54 +08:00
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* Intel SoC PMIC MFD Driver
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2014-06-03 13:26:02 +08:00
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*
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* Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#ifndef __INTEL_SOC_PMIC_CORE_H__
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#define __INTEL_SOC_PMIC_CORE_H__
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struct intel_soc_pmic_config {
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unsigned long irq_flags;
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struct mfd_cell *cell_dev;
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int n_cell_devs;
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2015-01-05 17:01:22 +08:00
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const struct regmap_config *regmap_config;
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2015-04-27 20:54:13 +08:00
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const struct regmap_irq_chip *irq_chip;
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2014-06-03 13:26:02 +08:00
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};
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mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT
Both Bay and Cherry Trail devices may be used together with a Crystal Cove
PMIC. Each platform has its own variant of the PMIC, which both use the
same ACPI HID, but they are not 100% compatible.
Looking at the android x86 kernel sources where most of the Crystal Cove
code comes from, it talks about "Valley View", "Bay Trail" and / or BYT
without ever mentioning Cherry Trail, with the exception of the regulator
driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one
for Crystal Cove and one for what it calls Crystal Cove Plus. The
Crystal Cove Plus regulator driver is the only one to mention Cherry
Trail and that driver uses different register addresses then the
normal (Bay Trail) Crystal Cove regulator driver, showing that at
least the regulator register addresses are different.
The GPIO code should work on both, and the PWM code is known to work on
both and is necessary for backlight control on some Cherry Trail devices.
Testing has shown that the ACPI OpRegion code otoh is causing problems
on Cherry Trail devices, which is not surprising as it deals with the
regulators and those have different register addresses on CHT.
Specifically the ACPI OpRegion code causes the external microsd slot on
a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to
become unreliable and throw lots of errors.
This commit replaces the single mfd_cell array currently used for Crystal
Cove with 2 separate arrays, one for the Bay Trail variant and one for
the Cherry Trail variant, note that the Cherry Trail version of the array
only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately
not included and drivers for the other cells in the Bay Trail cell array
were never upstreamed.
Fixes: 7cf0a66f32 ("mfd: intel_soc_pmic: Crystal Cove support")
Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-09-04 21:22:41 +08:00
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extern struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc;
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extern struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc;
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2014-06-03 13:26:02 +08:00
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#endif /* __INTEL_SOC_PMIC_CORE_H__ */
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