2010-08-24 11:24:12 +08:00
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/*
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* Linux network driver for Brocade Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*/
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#ifndef __BFA_DEFS_MFG_COMM_H__
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#define __BFA_DEFS_MFG_COMM_H__
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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#include "bfa_defs.h"
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2010-08-24 11:24:12 +08:00
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/**
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* Manufacturing block version
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*/
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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#define BFA_MFG_VERSION 3
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2010-08-24 11:24:12 +08:00
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#define BFA_MFG_VERSION_UNINIT 0xFF
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/**
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* Manufacturing block encrypted version
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*/
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#define BFA_MFG_ENC_VER 2
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/**
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* Manufacturing block version 1 length
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*/
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#define BFA_MFG_VER1_LEN 128
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/**
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* Manufacturing block header length
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*/
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#define BFA_MFG_HDR_LEN 4
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#define BFA_MFG_SERIALNUM_SIZE 11
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#define STRSZ(_n) (((_n) + 4) & ~3)
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/**
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* Manufacturing card type
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*/
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enum {
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BFA_MFG_TYPE_CB_MAX = 825, /*!< Crossbow card type max */
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BFA_MFG_TYPE_FC8P2 = 825, /*!< 8G 2port FC card */
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BFA_MFG_TYPE_FC8P1 = 815, /*!< 8G 1port FC card */
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BFA_MFG_TYPE_FC4P2 = 425, /*!< 4G 2port FC card */
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BFA_MFG_TYPE_FC4P1 = 415, /*!< 4G 1port FC card */
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BFA_MFG_TYPE_CNA10P2 = 1020, /*!< 10G 2port CNA card */
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BFA_MFG_TYPE_CNA10P1 = 1010, /*!< 10G 1port CNA card */
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BFA_MFG_TYPE_JAYHAWK = 804, /*!< Jayhawk mezz card */
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BFA_MFG_TYPE_WANCHESE = 1007, /*!< Wanchese mezz card */
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BFA_MFG_TYPE_ASTRA = 807, /*!< Astra mezz card */
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BFA_MFG_TYPE_LIGHTNING_P0 = 902, /*!< Lightning mezz card - old */
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BFA_MFG_TYPE_LIGHTNING = 1741, /*!< Lightning mezz card */
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BFA_MFG_TYPE_INVALID = 0, /*!< Invalid card type */
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};
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#pragma pack(1)
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/**
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* Check if Mezz card
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*/
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#define bfa_mfg_is_mezz(type) (( \
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(type) == BFA_MFG_TYPE_JAYHAWK || \
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(type) == BFA_MFG_TYPE_WANCHESE || \
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(type) == BFA_MFG_TYPE_ASTRA || \
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(type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
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(type) == BFA_MFG_TYPE_LIGHTNING))
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/**
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* Check if card type valid
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*/
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#define bfa_mfg_is_card_type_valid(type) (( \
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(type) == BFA_MFG_TYPE_FC8P2 || \
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(type) == BFA_MFG_TYPE_FC8P1 || \
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(type) == BFA_MFG_TYPE_FC4P2 || \
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(type) == BFA_MFG_TYPE_FC4P1 || \
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(type) == BFA_MFG_TYPE_CNA10P2 || \
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(type) == BFA_MFG_TYPE_CNA10P1 || \
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bfa_mfg_is_mezz(type)))
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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#define bfa_mfg_adapter_prop_init_flash_ct(mfgblk, prop) \
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2010-08-24 11:24:12 +08:00
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do { \
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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switch ((mfgblk)->card_type) { \
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2010-08-24 11:24:12 +08:00
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case BFA_MFG_TYPE_JAYHAWK: \
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case BFA_MFG_TYPE_ASTRA: \
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(prop) = BFI_ADAPTER_SETP(NPORTS, 2) | \
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BFI_ADAPTER_SETP(SPEED, 8); \
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break; \
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case BFA_MFG_TYPE_CNA10P2: \
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case BFA_MFG_TYPE_WANCHESE: \
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case BFA_MFG_TYPE_LIGHTNING_P0: \
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case BFA_MFG_TYPE_LIGHTNING: \
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(prop) = BFI_ADAPTER_SETP(NPORTS, 2); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 10); \
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break; \
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case BFA_MFG_TYPE_CNA10P1: \
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(prop) = BFI_ADAPTER_SETP(NPORTS, 1); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 10); \
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break; \
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default: \
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(prop) = BFI_ADAPTER_UNSUPP; \
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} \
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} while (0)
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enum {
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CB_GPIO_TTV = (1), /*!< TTV debug capable cards */
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CB_GPIO_FC8P2 = (2), /*!< 8G 2port FC card */
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CB_GPIO_FC8P1 = (3), /*!< 8G 1port FC card */
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CB_GPIO_FC4P2 = (4), /*!< 4G 2port FC card */
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CB_GPIO_FC4P1 = (5), /*!< 4G 1port FC card */
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CB_GPIO_DFLY = (6), /*!< 8G 2port FC mezzanine card */
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CB_GPIO_PROTO = (1 << 7) /*!< 8G 2port FC prototypes */
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};
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#define bfa_mfg_adapter_prop_init_gpio(gpio, card_type, prop) \
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do { \
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if ((gpio) & CB_GPIO_PROTO) { \
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(prop) |= BFI_ADAPTER_PROTO; \
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(gpio) &= ~CB_GPIO_PROTO; \
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} \
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switch ((gpio)) { \
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case CB_GPIO_TTV: \
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(prop) |= BFI_ADAPTER_TTV; \
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case CB_GPIO_DFLY: \
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case CB_GPIO_FC8P2: \
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(prop) |= BFI_ADAPTER_SETP(NPORTS, 2); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 8); \
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(card_type) = BFA_MFG_TYPE_FC8P2; \
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break; \
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case CB_GPIO_FC8P1: \
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(prop) |= BFI_ADAPTER_SETP(NPORTS, 1); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 8); \
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(card_type) = BFA_MFG_TYPE_FC8P1; \
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break; \
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case CB_GPIO_FC4P2: \
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(prop) |= BFI_ADAPTER_SETP(NPORTS, 2); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 4); \
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(card_type) = BFA_MFG_TYPE_FC4P2; \
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break; \
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case CB_GPIO_FC4P1: \
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(prop) |= BFI_ADAPTER_SETP(NPORTS, 1); \
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(prop) |= BFI_ADAPTER_SETP(SPEED, 4); \
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(card_type) = BFA_MFG_TYPE_FC4P1; \
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break; \
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default: \
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(prop) |= BFI_ADAPTER_UNSUPP; \
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(card_type) = BFA_MFG_TYPE_INVALID; \
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} \
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} while (0)
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/**
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* VPD data length
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*/
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#define BFA_MFG_VPD_LEN 512
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#define BFA_MFG_VPD_LEN_INVALID 0
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#define BFA_MFG_VPD_PCI_HDR_OFF 137
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#define BFA_MFG_VPD_PCI_VER_MASK 0x07 /*!< version mask 3 bits */
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#define BFA_MFG_VPD_PCI_VDR_MASK 0xf8 /*!< vendor mask 5 bits */
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/**
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* VPD vendor tag
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*/
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enum {
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2011-07-22 16:07:41 +08:00
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BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */
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BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */
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BFA_MFG_VPD_HP = 2, /*!< vendor HP */
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BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */
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BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */
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BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */
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BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */
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BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */
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2010-08-24 11:24:12 +08:00
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};
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/**
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* @brief BFA adapter flash vpd data definition.
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*
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* All numerical fields are in big-endian format.
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*/
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struct bfa_mfg_vpd {
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u8 version; /*!< vpd data version */
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u8 vpd_sig[3]; /*!< characters 'V', 'P', 'D' */
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u8 chksum; /*!< u8 checksum */
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u8 vendor; /*!< vendor */
|
2011-07-22 16:07:41 +08:00
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u8 len; /*!< vpd data length excluding header */
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u8 rsv;
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2010-08-24 11:24:12 +08:00
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u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */
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};
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#pragma pack()
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#endif /* __BFA_DEFS_MFG_H__ */
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