2015-01-30 02:10:50 +08:00
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#include <dt-bindings/pinctrl/bcm2835.h>
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ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
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#include <dt-bindings/clock/bcm2835.h>
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2015-01-30 02:10:50 +08:00
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#include "skeleton.dtsi"
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2012-05-26 15:04:43 +08:00
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/ {
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compatible = "brcm,bcm2835";
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model = "BCM2835";
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ARM: bcm2835: add interrupt controller driver
The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13 09:57:26 +08:00
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interrupt-parent = <&intc>;
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2012-05-26 15:04:43 +08:00
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chosen {
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2012-09-11 13:29:17 +08:00
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bootargs = "earlyprintk console=ttyAMA0";
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2012-05-26 15:04:43 +08:00
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x7e000000 0x20000000 0x02000000>;
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ARM: bcm2835: dt: Use 0x4 prefix for DMA bus addresses to SDRAM.
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in the bus address mean:
From the VideoCore processor:
0x0... L1 and L2 cache allocating and coherent
0x4... L1 non-allocating, but coherent. L2 allocating and coherent
0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
From the GPU peripherals (note: all peripherals bypass the L1
cache. The ARM will see this view once through the VC MMU):
0x0... Do not use
0x4... L1 non-allocating, and incoherent. L2 allocating and coherent.
0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent
0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent
The 2835 firmware always configures the MMU to turn ARM physical
addresses with 0x0 top bits to 0x4, meaning present in L2 but
incoherent with L1. However, any bus addresses we were generating in
the kernel to be passed to a device had 0x0 bits. That would be a
reserved (possibly totally incoherent) value if sent to a GPU
peripheral like USB, or L1 allocating if sent to the VC (like a
firmware property request). By setting dma-ranges, all of the devices
below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and
friends return addresses with 0x4 bits and avoid cache incoherency.
This matches the behavior in the downstream 2708 kernel (see
BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h).
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-05-06 04:10:11 +08:00
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dma-ranges = <0x40000000 0x00000000 0x20000000>;
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ARM: bcm2835: add interrupt controller driver
The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13 09:57:26 +08:00
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2014-02-12 12:48:47 +08:00
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timer@7e003000 {
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2012-09-11 12:38:35 +08:00
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7e003000 0x1000>;
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interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
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/* This could be a reference to BCM2835_CLOCK_TIMER,
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* but we don't have the driver using the common clock
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* support yet.
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*/
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2012-09-11 12:38:35 +08:00
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clock-frequency = <1000000>;
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};
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2014-01-13 19:11:43 +08:00
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dma: dma@7e007000 {
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compatible = "brcm,bcm2835-dma";
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reg = <0x7e007000 0xf00>;
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interrupts = <1 16>,
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<1 17>,
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<1 18>,
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<1 19>,
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<1 20>,
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<1 21>,
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<1 22>,
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<1 23>,
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<1 24>,
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<1 25>,
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<1 26>,
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<1 27>,
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<1 28>;
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#dma-cells = <1>;
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brcm,dma-channel-mask = <0x7f35>;
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};
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2014-02-12 12:48:47 +08:00
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intc: interrupt-controller@7e00b200 {
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ARM: bcm2835: add interrupt controller driver
The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13 09:57:26 +08:00
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compatible = "brcm,bcm2835-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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2012-09-11 13:29:17 +08:00
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2014-02-12 12:48:47 +08:00
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watchdog@7e100000 {
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2012-09-16 12:18:10 +08:00
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compatible = "brcm,bcm2835-pm-wdt";
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reg = <0x7e100000 0x28>;
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};
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ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
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clocks: cprman@7e101000 {
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compatible = "brcm,bcm2835-cprman";
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#clock-cells = <1>;
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reg = <0x7e101000 0x2000>;
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/* CPRMAN derives everything from the platform's
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* oscillator.
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*/
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clocks = <&clk_osc>;
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};
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2014-02-12 12:48:47 +08:00
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rng@7e104000 {
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2013-03-28 14:12:04 +08:00
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compatible = "brcm,bcm2835-rng";
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reg = <0x7e104000 0x10>;
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};
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2015-05-06 04:27:46 +08:00
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mailbox: mailbox@7e00b800 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7e00b880 0x40>;
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interrupts = <0 1>;
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#mbox-cells = <0>;
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};
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2014-02-12 12:48:47 +08:00
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gpio: gpio@7e200000 {
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2012-09-28 11:54:21 +08:00
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compatible = "brcm,bcm2835-gpio";
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reg = <0x7e200000 0xb4>;
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/*
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* The GPIO IP block is designed for 3 banks of GPIOs.
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* Each bank has a GPIO interrupt for itself.
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* There is an overall "any bank" interrupt.
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* In order, these are GIC interrupts 17, 18, 19, 20.
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* Since the BCM2835 only has 2 banks, the 2nd bank
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* interrupt output appears to be mirrored onto the
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* 3rd bank's interrupt signal.
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* So, a bank0 interrupt shows up on 17, 20, and
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* a bank1 interrupt shows up on 18, 19, 20!
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*/
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interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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2012-12-25 12:58:56 +08:00
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2015-10-03 02:31:15 +08:00
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uart0: uart@7e201000 {
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2014-02-12 12:44:35 +08:00
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compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
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reg = <0x7e201000 0x1000>;
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interrupts = <2 25>;
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ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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2014-02-12 12:44:35 +08:00
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arm,primecell-periphid = <0x00241011>;
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};
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2014-01-13 19:16:40 +08:00
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i2s: i2s@7e203000 {
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compatible = "brcm,bcm2835-i2s";
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reg = <0x7e203000 0x20>,
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<0x7e101098 0x02>;
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dmas = <&dma 2>,
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<&dma 3>;
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dma-names = "tx", "rx";
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2014-09-17 09:51:36 +08:00
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status = "disabled";
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2014-01-13 19:16:40 +08:00
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};
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2014-02-12 12:48:47 +08:00
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spi: spi@7e204000 {
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2013-02-20 12:39:58 +08:00
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204000 0x1000>;
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interrupts = <2 22>;
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ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
2013-02-20 12:39:58 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-03-18 17:00:22 +08:00
|
|
|
i2c0: i2c@7e205000 {
|
2013-01-01 14:26:45 +08:00
|
|
|
compatible = "brcm,bcm2835-i2c";
|
|
|
|
|
reg = <0x7e205000 0x1000>;
|
|
|
|
|
interrupts = <2 21>;
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
2013-11-26 11:35:42 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-01-01 14:26:45 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-12 12:48:47 +08:00
|
|
|
sdhci: sdhci@7e300000 {
|
2014-02-12 12:44:35 +08:00
|
|
|
compatible = "brcm,bcm2835-sdhci";
|
|
|
|
|
reg = <0x7e300000 0x100>;
|
|
|
|
|
interrupts = <2 30>;
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
clocks = <&clocks BCM2835_CLOCK_EMMC>;
|
2014-02-12 12:44:35 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-12 12:48:47 +08:00
|
|
|
i2c1: i2c@7e804000 {
|
2013-01-01 14:26:45 +08:00
|
|
|
compatible = "brcm,bcm2835-i2c";
|
|
|
|
|
reg = <0x7e804000 0x1000>;
|
|
|
|
|
interrupts = <2 21>;
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
2013-11-26 11:35:42 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-01-01 14:26:45 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-10-10 05:27:47 +08:00
|
|
|
i2c2: i2c@7e805000 {
|
|
|
|
|
compatible = "brcm,bcm2835-i2c";
|
|
|
|
|
reg = <0x7e805000 0x1000>;
|
|
|
|
|
interrupts = <2 21>;
|
|
|
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-12 12:48:47 +08:00
|
|
|
usb@7e980000 {
|
2013-12-27 10:43:10 +08:00
|
|
|
compatible = "brcm,bcm2835-usb";
|
|
|
|
|
reg = <0x7e980000 0x10000>;
|
|
|
|
|
interrupts = <1 9>;
|
|
|
|
|
};
|
2014-01-01 05:54:16 +08:00
|
|
|
|
|
|
|
|
arm-pmu {
|
|
|
|
|
compatible = "arm,arm1176-pmu";
|
|
|
|
|
};
|
2012-12-25 12:58:56 +08:00
|
|
|
};
|
|
|
|
|
|
2013-01-15 12:07:20 +08:00
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-01-01 14:26:45 +08:00
|
|
|
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
/* The oscillator is the root of the clock tree. */
|
|
|
|
|
clk_osc: clock@3 {
|
2013-01-15 12:07:20 +08:00
|
|
|
compatible = "fixed-clock";
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
reg = <3>;
|
2013-01-15 12:07:20 +08:00
|
|
|
#clock-cells = <0>;
|
ARM: bcm2835: Switch to using the new clock driver support.
This will give us the ability to set the pixel and HDMI state machine
clocks for the VC4 KMS driver, change the CPU frequency, and
potentially gate clocks in the future (once we also write a power
domain driver). It also gives the uart an explicit clock reference,
so that we don't need to change the physical addresses of the old
fixed clk_bcm2835.c clocks for Raspberry Pi 2 port.
Two clocks get their frequencies updated as a result of this. One is
uart's apb_pclk, which was previously accidentally grabbing the fixed
uart0_pclk due to the apb_pclk not having clk_register_clkdev()
called. The uart doesn't seem to do anything with apb_pclk other than
make sure it's on, so that appears safe (also, as far as I can see,
the apb clock is actually the same as the VPU clock). The other is
EMMC, which according to the docs was supposed to be in the 50-100Mhz
range, but it turns out the firmware needed to change to running it at
the 250Mhz core clock speed to avoid a bug in clock domain crossing.
Additionally, anything using BCM2835_CLOCK_VPU will now have a correct
clock rate if the user configures the boot-time core clock speed using
config.txt.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-09-29 05:22:05 +08:00
|
|
|
clock-output-names = "osc";
|
|
|
|
|
clock-frequency = <19200000>;
|
2013-01-15 12:07:20 +08:00
|
|
|
};
|
2013-02-20 12:39:58 +08:00
|
|
|
|
2012-05-26 15:04:43 +08:00
|
|
|
};
|
|
|
|
|
};
|