2007-10-10 23:55:26 +08:00
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/*
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2009-09-24 22:11:24 +08:00
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* Copyright 2004-2009 Analog Devices Inc.
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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*
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2009-09-24 22:11:24 +08:00
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* Licensed under the GPL-2 or later.
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2007-10-10 23:55:26 +08:00
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*/
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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#ifndef _CPLB_H
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#define _CPLB_H
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2008-08-27 10:51:02 +08:00
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#include <mach/anomaly.h>
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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2007-10-10 23:55:26 +08:00
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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#if ANOMALY_05000158
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#define ANOMALY_05000158_WORKAROUND 0x200
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#else
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#define ANOMALY_05000158_WORKAROUND 0x0
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#endif
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#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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2009-06-16 17:48:33 +08:00
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#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
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2007-10-10 23:55:26 +08:00
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
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2009-06-16 17:48:33 +08:00
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#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
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2007-10-10 23:55:26 +08:00
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
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2009-06-16 17:48:33 +08:00
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#else
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#define SDRAM_DGENERIC (CPLB_COMMON)
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2007-10-10 23:55:26 +08:00
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#endif
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2009-05-07 12:09:15 +08:00
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#define SDRAM_DNON_CHBL (CPLB_COMMON)
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#define SDRAM_EBIU (CPLB_COMMON)
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
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2007-10-10 23:55:26 +08:00
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#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
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2008-11-18 17:48:22 +08:00
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#ifdef CONFIG_SMP
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2009-05-07 12:09:15 +08:00
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#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
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2009-06-16 17:48:33 +08:00
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#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
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#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
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2008-11-18 17:48:22 +08:00
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#else
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2009-05-07 12:09:15 +08:00
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#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
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2009-06-16 17:48:33 +08:00
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# if defined(CONFIG_BFIN_L2_ICACHEABLE)
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# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
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# else
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# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
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# endif
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2009-05-07 12:09:15 +08:00
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2009-06-16 17:48:33 +08:00
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# if defined(CONFIG_BFIN_L2_WRITEBACK)
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# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
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# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
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# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
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2009-05-07 12:09:15 +08:00
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# else
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2009-06-16 17:48:33 +08:00
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# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
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2009-05-07 12:09:15 +08:00
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# endif
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2008-11-18 17:48:22 +08:00
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#endif /* CONFIG_SMP */
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2007-10-10 23:55:26 +08:00
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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2008-01-27 18:39:16 +08:00
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#define MAX_CPLBS 16
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2007-08-27 15:29:35 +08:00
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
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#define CPLB_ENABLE_ICPLBS_P 4
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#define CPLB_ENABLE_DCPLBS_P 5
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#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
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#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
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#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
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#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
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#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
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#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
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#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
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CPLB_ENABLE_ICPLBS | \
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CPLB_ENABLE_DCPLBS
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#define CPLB_RELOADED 0x0000
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#define CPLB_NO_UNLOCKED 0x0001
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#define CPLB_NO_ADDR_MATCH 0x0002
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#define CPLB_PROT_VIOL 0x0003
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#define CPLB_UNKNOWN_ERR 0x0004
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#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
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#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
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#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
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#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
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#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
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#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
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2009-01-07 23:14:38 +08:00
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#define FAULT_RW (1 << 16)
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#define FAULT_USERSUPV (1 << 17)
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#define FAULT_CPLBBITS 0x0000ffff
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2009-08-07 09:20:58 +08:00
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#ifndef __ASSEMBLY__
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static inline void _disable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) & ~mask;
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/* CSYNC to ensure load store ordering */
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__builtin_bfin_csync();
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bfin_write32(mmr, ctrl);
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__builtin_bfin_ssync();
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}
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static inline void disable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) & ~mask;
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CSYNC();
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bfin_write32(mmr, ctrl);
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SSYNC();
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}
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#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
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#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
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#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
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#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
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static inline void _enable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) | mask;
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/* CSYNC to ensure load store ordering */
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__builtin_bfin_csync();
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bfin_write32(mmr, ctrl);
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__builtin_bfin_ssync();
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}
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static inline void enable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) | mask;
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CSYNC();
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bfin_write32(mmr, ctrl);
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SSYNC();
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}
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#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
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#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
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#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
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#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
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#endif /* __ASSEMBLY__ */
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#endif /* _CPLB_H */
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