linux/drivers/clk/meson/Makefile

#
# Makefile for Meson specific clk
#

obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o
clk: meson: Add support for Meson clock controller This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-06-01 19:13:53 +08:00			`#`
			`# Makefile for Meson specific clk`
			`#`

clk: meson: add mpll support MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-06-07 14:16:17 +08:00			`obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o`
clk: meson: only build selected platforms Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 05:29:13 +08:00			`obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o`
clk: gxbb: add AmLogic GXBB clk controller driver The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> 2016-05-24 06:44:26 +08:00			`obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o`