2008-05-20 07:52:27 +08:00
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/*
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2005-04-17 06:20:36 +08:00
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* unaligned.c: Unaligned load/store trap handling with special
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* cases for the kernel to do them more quickly.
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*
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2008-07-18 13:11:32 +08:00
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* Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
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2005-04-17 06:20:36 +08:00
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* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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2008-02-18 15:24:10 +08:00
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#include <linux/jiffies.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <asm/asi.h>
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#include <asm/ptrace.h>
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#include <asm/pstate.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <linux/smp.h>
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#include <linux/bitops.h>
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2009-12-11 17:07:53 +08:00
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#include <linux/perf_event.h>
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2010-02-28 19:31:29 +08:00
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#include <linux/ratelimit.h>
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2013-09-14 20:02:11 +08:00
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#include <linux/context_tracking.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/fpumacro.h>
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2012-03-29 01:30:03 +08:00
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#include <asm/cacheflush.h>
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2014-05-17 05:25:54 +08:00
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#include <asm/setup.h>
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2005-04-17 06:20:36 +08:00
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2013-09-14 20:02:11 +08:00
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#include "entry.h"
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2014-05-17 05:25:54 +08:00
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#include "kernel.h"
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2013-09-14 20:02:11 +08:00
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2005-04-17 06:20:36 +08:00
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enum direction {
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load, /* ld, ldd, ldh, ldsh */
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store, /* st, std, sth, stsh */
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both, /* Swap, ldstub, cas, ... */
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fpld,
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fpst,
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invalid,
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};
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static inline enum direction decode_direction(unsigned int insn)
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{
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unsigned long tmp = (insn >> 21) & 1;
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if (!tmp)
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return load;
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else {
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switch ((insn>>19)&0xf) {
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case 15: /* swap* */
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return both;
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default:
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return store;
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}
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}
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}
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/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
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2010-04-20 04:46:48 +08:00
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static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
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2005-04-17 06:20:36 +08:00
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{
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unsigned int tmp;
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tmp = ((insn >> 19) & 0xf);
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if (tmp == 11 || tmp == 14) /* ldx/stx */
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return 8;
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tmp &= 3;
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if (!tmp)
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return 4;
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else if (tmp == 3)
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return 16; /* ldd/std - Although it is actually 8 */
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else if (tmp == 2)
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return 2;
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else {
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printk("Impossible unaligned trap. insn=%08x\n", insn);
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2010-04-20 04:46:48 +08:00
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die_if_kernel("Byte sized unaligned access?!?!", regs);
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2005-04-17 06:20:36 +08:00
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/* GCC should never warn that control reaches the end
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* of this function without returning a value because
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* die_if_kernel() is marked with attribute 'noreturn'.
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* Alas, some versions do...
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*/
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return 0;
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}
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}
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static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
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{
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if (insn & 0x800000) {
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if (insn & 0x2000)
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return (unsigned char)(regs->tstate >> 24); /* %asi */
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else
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return (unsigned char)(insn >> 5); /* imm_asi */
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} else
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return ASI_P;
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}
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/* 0x400000 = signed, 0 = unsigned */
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static inline int decode_signedness(unsigned int insn)
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{
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return (insn & 0x400000);
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}
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static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
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unsigned int rd, int from_kernel)
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{
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if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
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if (from_kernel != 0)
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__asm__ __volatile__("flushw");
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else
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flushw_user();
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}
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}
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static inline long sign_extend_imm13(long imm)
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{
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return imm << 51 >> 51;
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}
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static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
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{
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sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
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unsigned long value, fp;
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2005-04-17 06:20:36 +08:00
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if (reg < 16)
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return (!reg ? 0 : regs->u_regs[reg]);
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sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
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fp = regs->u_regs[UREG_FP];
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2005-04-17 06:20:36 +08:00
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if (regs->tstate & TSTATE_PRIV) {
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struct reg_window *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
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win = (struct reg_window *)(fp + STACK_BIAS);
|
2005-04-17 06:20:36 +08:00
|
|
|
value = win->locals[reg - 16];
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
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} else if (!test_thread_64bit_stack(fp)) {
|
2005-04-17 06:20:36 +08:00
|
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struct reg_window32 __user *win32;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
|
2005-04-17 06:20:36 +08:00
|
|
|
get_user(value, &win32->locals[reg - 16]);
|
|
|
|
|
} else {
|
|
|
|
|
struct reg_window __user *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win = (struct reg_window __user *)(fp + STACK_BIAS);
|
2005-04-17 06:20:36 +08:00
|
|
|
get_user(value, &win->locals[reg - 16]);
|
|
|
|
|
}
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
|
|
|
|
|
{
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
unsigned long fp;
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if (reg < 16)
|
|
|
|
|
return ®s->u_regs[reg];
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
|
|
|
|
|
fp = regs->u_regs[UREG_FP];
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if (regs->tstate & TSTATE_PRIV) {
|
|
|
|
|
struct reg_window *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win = (struct reg_window *)(fp + STACK_BIAS);
|
2005-04-17 06:20:36 +08:00
|
|
|
return &win->locals[reg - 16];
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
} else if (!test_thread_64bit_stack(fp)) {
|
2005-04-17 06:20:36 +08:00
|
|
|
struct reg_window32 *win32;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
|
2005-04-17 06:20:36 +08:00
|
|
|
return (unsigned long *)&win32->locals[reg - 16];
|
|
|
|
|
} else {
|
|
|
|
|
struct reg_window *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win = (struct reg_window *)(fp + STACK_BIAS);
|
2005-04-17 06:20:36 +08:00
|
|
|
return &win->locals[reg - 16];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned long compute_effective_address(struct pt_regs *regs,
|
|
|
|
|
unsigned int insn, unsigned int rd)
|
|
|
|
|
{
|
2014-04-29 14:50:08 +08:00
|
|
|
int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int rs1 = (insn >> 14) & 0x1f;
|
|
|
|
|
unsigned int rs2 = insn & 0x1f;
|
2014-04-29 14:50:08 +08:00
|
|
|
unsigned long addr;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
if (insn & 0x2000) {
|
|
|
|
|
maybe_flush_windows(rs1, 0, rd, from_kernel);
|
2014-04-29 14:50:08 +08:00
|
|
|
addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
|
|
|
|
maybe_flush_windows(rs1, rs2, rd, from_kernel);
|
2014-04-29 14:50:08 +08:00
|
|
|
addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2014-04-29 14:50:08 +08:00
|
|
|
|
|
|
|
|
if (!from_kernel && test_thread_flag(TIF_32BIT))
|
|
|
|
|
addr &= 0xffffffff;
|
|
|
|
|
|
|
|
|
|
return addr;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This is just to make gcc think die_if_kernel does return... */
|
2008-01-25 05:16:20 +08:00
|
|
|
static void __used unaligned_panic(char *str, struct pt_regs *regs)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
|
die_if_kernel(str, regs);
|
|
|
|
|
}
|
|
|
|
|
|
2005-09-29 11:41:45 +08:00
|
|
|
extern int do_int_load(unsigned long *dest_reg, int size,
|
|
|
|
|
unsigned long *saddr, int is_signed, int asi);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-09-29 11:41:45 +08:00
|
|
|
extern int __do_int_store(unsigned long *dst_addr, int size,
|
|
|
|
|
unsigned long src_val, int asi);
|
2005-08-20 06:55:33 +08:00
|
|
|
|
2005-09-29 11:41:45 +08:00
|
|
|
static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
|
|
|
|
|
struct pt_regs *regs, int asi, int orig_asi)
|
2005-08-20 06:55:33 +08:00
|
|
|
{
|
|
|
|
|
unsigned long zero = 0;
|
2005-09-20 10:56:06 +08:00
|
|
|
unsigned long *src_val_p = &zero;
|
|
|
|
|
unsigned long src_val;
|
2005-08-20 06:55:33 +08:00
|
|
|
|
|
|
|
|
if (size == 16) {
|
|
|
|
|
size = 8;
|
|
|
|
|
zero = (((long)(reg_num ?
|
2016-03-11 07:21:43 +08:00
|
|
|
(unsigned int)fetch_reg(reg_num, regs) : 0)) << 32) |
|
|
|
|
|
(unsigned int)fetch_reg(reg_num + 1, regs);
|
2005-08-20 06:55:33 +08:00
|
|
|
} else if (reg_num) {
|
2005-09-20 10:56:06 +08:00
|
|
|
src_val_p = fetch_reg_addr(reg_num, regs);
|
|
|
|
|
}
|
|
|
|
|
src_val = *src_val_p;
|
|
|
|
|
if (unlikely(asi != orig_asi)) {
|
|
|
|
|
switch (size) {
|
|
|
|
|
case 2:
|
|
|
|
|
src_val = swab16(src_val);
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
src_val = swab32(src_val);
|
|
|
|
|
break;
|
|
|
|
|
case 8:
|
|
|
|
|
src_val = swab64(src_val);
|
|
|
|
|
break;
|
|
|
|
|
case 16:
|
|
|
|
|
default:
|
|
|
|
|
BUG();
|
|
|
|
|
break;
|
2011-06-03 22:45:23 +08:00
|
|
|
}
|
2005-08-20 06:55:33 +08:00
|
|
|
}
|
2005-09-29 11:41:45 +08:00
|
|
|
return __do_int_store(dst_addr, size, src_val, asi);
|
2005-08-20 06:55:33 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
static inline void advance(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
regs->tpc = regs->tnpc;
|
|
|
|
|
regs->tnpc += 4;
|
|
|
|
|
if (test_thread_flag(TIF_32BIT)) {
|
|
|
|
|
regs->tpc &= 0xffffffff;
|
|
|
|
|
regs->tnpc &= 0xffffffff;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int floating_point_load_or_store_p(unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
return (insn >> 24) & 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int ok_for_kernel(unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
return !floating_point_load_or_store_p(insn);
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-29 12:18:05 +08:00
|
|
|
static void kernel_mna_trap_fault(int fixup_tstate_asi)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-08-20 06:55:33 +08:00
|
|
|
struct pt_regs *regs = current_thread_info()->kern_una_regs;
|
|
|
|
|
unsigned int insn = current_thread_info()->kern_una_insn;
|
2005-09-29 11:21:11 +08:00
|
|
|
const struct exception_table_entry *entry;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-09-29 11:21:11 +08:00
|
|
|
entry = search_exception_tables(regs->tpc);
|
|
|
|
|
if (!entry) {
|
2005-08-20 06:55:33 +08:00
|
|
|
unsigned long address;
|
|
|
|
|
|
|
|
|
|
address = compute_effective_address(regs, insn,
|
|
|
|
|
((insn >> 25) & 0x1f));
|
2005-04-17 06:20:36 +08:00
|
|
|
if (address < PAGE_SIZE) {
|
2005-08-20 06:55:33 +08:00
|
|
|
printk(KERN_ALERT "Unable to handle kernel NULL "
|
|
|
|
|
"pointer dereference in mna handler");
|
2005-04-17 06:20:36 +08:00
|
|
|
} else
|
2005-08-20 06:55:33 +08:00
|
|
|
printk(KERN_ALERT "Unable to handle kernel paging "
|
|
|
|
|
"request in mna handler");
|
2005-04-17 06:20:36 +08:00
|
|
|
printk(KERN_ALERT " at virtual address %016lx\n",address);
|
2005-08-20 06:55:33 +08:00
|
|
|
printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
|
2005-04-17 06:20:36 +08:00
|
|
|
(current->mm ? CTX_HWBITS(current->mm->context) :
|
|
|
|
|
CTX_HWBITS(current->active_mm->context)));
|
2005-08-20 06:55:33 +08:00
|
|
|
printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
|
2005-04-17 06:20:36 +08:00
|
|
|
(current->mm ? (unsigned long) current->mm->pgd :
|
|
|
|
|
(unsigned long) current->active_mm->pgd));
|
|
|
|
|
die_if_kernel("Oops", regs);
|
|
|
|
|
/* Not reached */
|
|
|
|
|
}
|
2005-09-29 11:21:11 +08:00
|
|
|
regs->tpc = entry->fixup;
|
2005-04-17 06:20:36 +08:00
|
|
|
regs->tnpc = regs->tpc + 4;
|
|
|
|
|
|
2006-11-29 12:18:05 +08:00
|
|
|
if (fixup_tstate_asi) {
|
|
|
|
|
regs->tstate &= ~TSTATE_ASI;
|
|
|
|
|
regs->tstate |= (ASI_AIUS << 24UL);
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
2006-11-29 12:18:05 +08:00
|
|
|
static void log_unaligned(struct pt_regs *regs)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2010-02-28 19:31:29 +08:00
|
|
|
static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
|
2005-08-20 06:55:33 +08:00
|
|
|
|
2010-02-28 19:31:29 +08:00
|
|
|
if (__ratelimit(&ratelimit)) {
|
2008-07-18 13:11:32 +08:00
|
|
|
printk("Kernel unaligned access at TPC[%lx] %pS\n",
|
|
|
|
|
regs->tpc, (void *) regs->tpc);
|
2006-06-22 13:31:08 +08:00
|
|
|
}
|
2006-11-29 12:18:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
enum direction dir = decode_direction(insn);
|
2010-04-20 04:46:48 +08:00
|
|
|
int size = decode_access_size(regs, insn);
|
2006-11-29 12:18:05 +08:00
|
|
|
int orig_asi, asi;
|
|
|
|
|
|
|
|
|
|
current_thread_info()->kern_una_regs = regs;
|
|
|
|
|
current_thread_info()->kern_una_insn = insn;
|
|
|
|
|
|
|
|
|
|
orig_asi = asi = decode_asi(insn, regs);
|
|
|
|
|
|
|
|
|
|
/* If this is a {get,put}_user() on an unaligned userspace pointer,
|
|
|
|
|
* just signal a fault and do not log the event.
|
|
|
|
|
*/
|
|
|
|
|
if (asi == ASI_AIUS) {
|
|
|
|
|
kernel_mna_trap_fault(0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
log_unaligned(regs);
|
2006-06-22 13:31:08 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!ok_for_kernel(insn) || dir == both) {
|
2005-08-20 06:55:33 +08:00
|
|
|
printk("Unsupported unaligned load/store trap for kernel "
|
|
|
|
|
"at <%016lx>.\n", regs->tpc);
|
|
|
|
|
unaligned_panic("Kernel does fpu/atomic "
|
|
|
|
|
"unaligned load/store.", regs);
|
|
|
|
|
|
2006-11-29 12:18:05 +08:00
|
|
|
kernel_mna_trap_fault(0);
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2005-09-29 07:48:40 +08:00
|
|
|
unsigned long addr, *reg_addr;
|
2006-11-29 12:18:05 +08:00
|
|
|
int err;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-08-20 06:55:33 +08:00
|
|
|
addr = compute_effective_address(regs, insn,
|
|
|
|
|
((insn >> 25) & 0x1f));
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
|
2005-09-20 10:56:06 +08:00
|
|
|
switch (asi) {
|
|
|
|
|
case ASI_NL:
|
|
|
|
|
case ASI_AIUPL:
|
|
|
|
|
case ASI_AIUSL:
|
|
|
|
|
case ASI_PL:
|
|
|
|
|
case ASI_SL:
|
|
|
|
|
case ASI_PNFL:
|
|
|
|
|
case ASI_SNFL:
|
|
|
|
|
asi &= ~0x08;
|
|
|
|
|
break;
|
2011-06-03 22:45:23 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
switch (dir) {
|
|
|
|
|
case load:
|
2005-09-29 07:48:40 +08:00
|
|
|
reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
|
2005-09-29 11:41:45 +08:00
|
|
|
err = do_int_load(reg_addr, size,
|
|
|
|
|
(unsigned long *) addr,
|
|
|
|
|
decode_signedness(insn), asi);
|
|
|
|
|
if (likely(!err) && unlikely(asi != orig_asi)) {
|
2005-09-29 07:48:40 +08:00
|
|
|
unsigned long val_in = *reg_addr;
|
2005-09-20 10:56:06 +08:00
|
|
|
switch (size) {
|
|
|
|
|
case 2:
|
|
|
|
|
val_in = swab16(val_in);
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
val_in = swab32(val_in);
|
|
|
|
|
break;
|
|
|
|
|
case 8:
|
|
|
|
|
val_in = swab64(val_in);
|
|
|
|
|
break;
|
|
|
|
|
case 16:
|
|
|
|
|
default:
|
|
|
|
|
BUG();
|
|
|
|
|
break;
|
2011-06-03 22:45:23 +08:00
|
|
|
}
|
2005-09-29 07:48:40 +08:00
|
|
|
*reg_addr = val_in;
|
2005-09-20 10:56:06 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case store:
|
2005-09-29 11:41:45 +08:00
|
|
|
err = do_int_store(((insn>>25)&0x1f), size,
|
|
|
|
|
(unsigned long *) addr, regs,
|
|
|
|
|
asi, orig_asi);
|
2005-04-17 06:20:36 +08:00
|
|
|
break;
|
2005-08-20 06:55:33 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
default:
|
|
|
|
|
panic("Impossible kernel unaligned trap.");
|
|
|
|
|
/* Not reached... */
|
|
|
|
|
}
|
2005-09-29 11:41:45 +08:00
|
|
|
if (unlikely(err))
|
2006-11-29 12:18:05 +08:00
|
|
|
kernel_mna_trap_fault(1);
|
2005-09-29 11:41:45 +08:00
|
|
|
else
|
|
|
|
|
advance(regs);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int handle_popc(u32 insn, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
|
2011-08-02 10:41:12 +08:00
|
|
|
int ret, rd = ((insn >> 25) & 0x1f);
|
|
|
|
|
u64 value;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (insn & 0x2000) {
|
|
|
|
|
maybe_flush_windows(0, 0, rd, from_kernel);
|
|
|
|
|
value = sign_extend_imm13(insn);
|
|
|
|
|
} else {
|
|
|
|
|
maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
|
|
|
|
|
value = fetch_reg(insn & 0x1f, regs);
|
|
|
|
|
}
|
2011-08-02 10:41:12 +08:00
|
|
|
ret = hweight64(value);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (rd < 16) {
|
|
|
|
|
if (rd)
|
|
|
|
|
regs->u_regs[rd] = ret;
|
|
|
|
|
} else {
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
unsigned long fp = regs->u_regs[UREG_FP];
|
|
|
|
|
|
|
|
|
|
if (!test_thread_64bit_stack(fp)) {
|
2005-04-17 06:20:36 +08:00
|
|
|
struct reg_window32 __user *win32;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
|
2005-04-17 06:20:36 +08:00
|
|
|
put_user(ret, &win32->locals[rd - 16]);
|
|
|
|
|
} else {
|
|
|
|
|
struct reg_window __user *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
win = (struct reg_window __user *)(fp + STACK_BIAS);
|
2005-04-17 06:20:36 +08:00
|
|
|
put_user(ret, &win->locals[rd - 16]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
advance(regs);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
extern void do_fpother(struct pt_regs *regs);
|
|
|
|
|
extern void do_privact(struct pt_regs *regs);
|
2006-02-10 12:20:34 +08:00
|
|
|
extern void sun4v_data_access_exception(struct pt_regs *regs,
|
|
|
|
|
unsigned long addr,
|
|
|
|
|
unsigned long type_ctx);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
int handle_ldf_stq(u32 insn, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
unsigned long addr = compute_effective_address(regs, insn, 0);
|
sparc64: Don't restrict fp regs for no-fault loads
The function handle_ldf_stq() deals with no-fault ASI
loads and stores, but restricts fp registers to quad
word regs (ie, %f0, %f4 etc). This is valid for the
STQ case, but unnecessarily restricts loads, which
may be single precision, double, or quad. This results
in SIGFPE being raised for this instruction when the
source address is invalid:
ldda [%g1] ASI_PNF, %f2
but not for this one:
ldda [%g1] ASI_PNF, %f4
The validation check for quad register is moved to
within the STQ block so that loads are not affected
by the check.
An additional problem is that the calculation for freg
is incorrect when a single precision load is being
handled. This causes %f1 to be seen as %f32 etc,
and the incorrect register ends up being overwritten.
This code sequence demonstrates the problem:
ldd [%g1], %f32 ! g1 = valid address
lda [%i3] ASI_PNF, %f1 ! i3 = invalid address
std %f32, [%g1]
This is corrected by basing the freg calculation on
the load size.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-31 12:36:23 +08:00
|
|
|
int freg;
|
2005-04-17 06:20:36 +08:00
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
int asi = decode_asi(insn, regs);
|
sparc64: Don't restrict fp regs for no-fault loads
The function handle_ldf_stq() deals with no-fault ASI
loads and stores, but restricts fp registers to quad
word regs (ie, %f0, %f4 etc). This is valid for the
STQ case, but unnecessarily restricts loads, which
may be single precision, double, or quad. This results
in SIGFPE being raised for this instruction when the
source address is invalid:
ldda [%g1] ASI_PNF, %f2
but not for this one:
ldda [%g1] ASI_PNF, %f4
The validation check for quad register is moved to
within the STQ block so that loads are not affected
by the check.
An additional problem is that the calculation for freg
is incorrect when a single precision load is being
handled. This causes %f1 to be seen as %f32 etc,
and the incorrect register ends up being overwritten.
This code sequence demonstrates the problem:
ldd [%g1], %f32 ! g1 = valid address
lda [%i3] ASI_PNF, %f1 ! i3 = invalid address
std %f32, [%g1]
This is corrected by basing the freg calculation on
the load size.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-31 12:36:23 +08:00
|
|
|
int flag;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
2009-12-11 17:07:53 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
save_and_clear_fpu();
|
|
|
|
|
current_thread_info()->xfsr[0] &= ~0x1c000;
|
|
|
|
|
if (insn & 0x200000) {
|
|
|
|
|
/* STQ */
|
|
|
|
|
u64 first = 0, second = 0;
|
|
|
|
|
|
sparc64: Don't restrict fp regs for no-fault loads
The function handle_ldf_stq() deals with no-fault ASI
loads and stores, but restricts fp registers to quad
word regs (ie, %f0, %f4 etc). This is valid for the
STQ case, but unnecessarily restricts loads, which
may be single precision, double, or quad. This results
in SIGFPE being raised for this instruction when the
source address is invalid:
ldda [%g1] ASI_PNF, %f2
but not for this one:
ldda [%g1] ASI_PNF, %f4
The validation check for quad register is moved to
within the STQ block so that loads are not affected
by the check.
An additional problem is that the calculation for freg
is incorrect when a single precision load is being
handled. This causes %f1 to be seen as %f32 etc,
and the incorrect register ends up being overwritten.
This code sequence demonstrates the problem:
ldd [%g1], %f32 ! g1 = valid address
lda [%i3] ASI_PNF, %f1 ! i3 = invalid address
std %f32, [%g1]
This is corrected by basing the freg calculation on
the load size.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-31 12:36:23 +08:00
|
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
|
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
|
|
|
if (freg & 3) {
|
|
|
|
|
current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
|
|
|
|
|
do_fpother(regs);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
if (current_thread_info()->fpsaved[0] & flag) {
|
|
|
|
|
first = *(u64 *)&f->regs[freg];
|
|
|
|
|
second = *(u64 *)&f->regs[freg+2];
|
|
|
|
|
}
|
|
|
|
|
if (asi < 0x80) {
|
|
|
|
|
do_privact(regs);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
switch (asi) {
|
|
|
|
|
case ASI_P:
|
|
|
|
|
case ASI_S: break;
|
|
|
|
|
case ASI_PL:
|
|
|
|
|
case ASI_SL:
|
|
|
|
|
{
|
|
|
|
|
/* Need to convert endians */
|
|
|
|
|
u64 tmp = __swab64p(&first);
|
|
|
|
|
|
|
|
|
|
first = __swab64p(&second);
|
|
|
|
|
second = tmp;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
2006-02-10 12:20:34 +08:00
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, addr, 0);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, 0, addr);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
if (put_user (first >> 32, (u32 __user *)addr) ||
|
|
|
|
|
__put_user ((u32)first, (u32 __user *)(addr + 4)) ||
|
|
|
|
|
__put_user (second >> 32, (u32 __user *)(addr + 8)) ||
|
|
|
|
|
__put_user ((u32)second, (u32 __user *)(addr + 12))) {
|
2006-02-10 12:20:34 +08:00
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, addr, 0);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, 0, addr);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
/* LDF, LDDF, LDQF */
|
|
|
|
|
u32 data[4] __attribute__ ((aligned(8)));
|
|
|
|
|
int size, i;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (asi < 0x80) {
|
|
|
|
|
do_privact(regs);
|
|
|
|
|
return 1;
|
|
|
|
|
} else if (asi > ASI_SNFL) {
|
2006-02-10 12:20:34 +08:00
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, addr, 0);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, 0, addr);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
switch (insn & 0x180000) {
|
|
|
|
|
case 0x000000: size = 1; break;
|
|
|
|
|
case 0x100000: size = 4; break;
|
|
|
|
|
default: size = 2; break;
|
|
|
|
|
}
|
sparc64: Don't restrict fp regs for no-fault loads
The function handle_ldf_stq() deals with no-fault ASI
loads and stores, but restricts fp registers to quad
word regs (ie, %f0, %f4 etc). This is valid for the
STQ case, but unnecessarily restricts loads, which
may be single precision, double, or quad. This results
in SIGFPE being raised for this instruction when the
source address is invalid:
ldda [%g1] ASI_PNF, %f2
but not for this one:
ldda [%g1] ASI_PNF, %f4
The validation check for quad register is moved to
within the STQ block so that loads are not affected
by the check.
An additional problem is that the calculation for freg
is incorrect when a single precision load is being
handled. This causes %f1 to be seen as %f32 etc,
and the incorrect register ends up being overwritten.
This code sequence demonstrates the problem:
ldd [%g1], %f32 ! g1 = valid address
lda [%i3] ASI_PNF, %f1 ! i3 = invalid address
std %f32, [%g1]
This is corrected by basing the freg calculation on
the load size.
Signed-off-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-31 12:36:23 +08:00
|
|
|
if (size == 1)
|
|
|
|
|
freg = (insn >> 25) & 0x1f;
|
|
|
|
|
else
|
|
|
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
|
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
for (i = 0; i < size; i++)
|
|
|
|
|
data[i] = 0;
|
|
|
|
|
|
|
|
|
|
err = get_user (data[0], (u32 __user *) addr);
|
|
|
|
|
if (!err) {
|
|
|
|
|
for (i = 1; i < size; i++)
|
|
|
|
|
err |= __get_user (data[i], (u32 __user *)(addr + 4*i));
|
|
|
|
|
}
|
|
|
|
|
if (err && !(asi & 0x2 /* NF */)) {
|
2006-02-10 12:20:34 +08:00
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, addr, 0);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, 0, addr);
|
2005-04-17 06:20:36 +08:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
if (asi & 0x8) /* Little */ {
|
|
|
|
|
u64 tmp;
|
|
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
|
case 1: data[0] = le32_to_cpup(data + 0); break;
|
|
|
|
|
default:*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 0));
|
|
|
|
|
break;
|
|
|
|
|
case 4: tmp = le64_to_cpup((u64 *)(data + 0));
|
|
|
|
|
*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 2));
|
|
|
|
|
*(u64 *)(data + 2) = tmp;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
|
|
|
|
|
current_thread_info()->fpsaved[0] = FPRS_FEF;
|
|
|
|
|
current_thread_info()->gsr[0] = 0;
|
|
|
|
|
}
|
|
|
|
|
if (!(current_thread_info()->fpsaved[0] & flag)) {
|
|
|
|
|
if (freg < 32)
|
|
|
|
|
memset(f->regs, 0, 32*sizeof(u32));
|
|
|
|
|
else
|
|
|
|
|
memset(f->regs+32, 0, 32*sizeof(u32));
|
|
|
|
|
}
|
|
|
|
|
memcpy(f->regs + freg, data, size * 4);
|
|
|
|
|
current_thread_info()->fpsaved[0] |= flag;
|
|
|
|
|
}
|
|
|
|
|
advance(regs);
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void handle_ld_nf(u32 insn, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
int rd = ((insn >> 25) & 0x1f);
|
|
|
|
|
int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
|
|
|
|
|
unsigned long *reg;
|
|
|
|
|
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
2009-12-11 17:07:53 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
maybe_flush_windows(0, 0, rd, from_kernel);
|
|
|
|
|
reg = fetch_reg_addr(rd, regs);
|
|
|
|
|
if (from_kernel || rd < 16) {
|
|
|
|
|
reg[0] = 0;
|
|
|
|
|
if ((insn & 0x780000) == 0x180000)
|
|
|
|
|
reg[1] = 0;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 06:18:37 +08:00
|
|
|
} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
|
2005-04-17 06:20:36 +08:00
|
|
|
put_user(0, (int __user *) reg);
|
|
|
|
|
if ((insn & 0x780000) == 0x180000)
|
|
|
|
|
put_user(0, ((int __user *) reg) + 1);
|
|
|
|
|
} else {
|
|
|
|
|
put_user(0, (unsigned long __user *) reg);
|
|
|
|
|
if ((insn & 0x780000) == 0x180000)
|
|
|
|
|
put_user(0, (unsigned long __user *) reg + 1);
|
|
|
|
|
}
|
|
|
|
|
advance(regs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
|
|
|
|
|
{
|
2013-09-14 20:02:11 +08:00
|
|
|
enum ctx_state prev_state = exception_enter();
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long pc = regs->tpc;
|
|
|
|
|
unsigned long tstate = regs->tstate;
|
|
|
|
|
u32 insn;
|
|
|
|
|
u64 value;
|
2006-02-10 12:20:34 +08:00
|
|
|
u8 freg;
|
2005-04-17 06:20:36 +08:00
|
|
|
int flag;
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
|
|
|
|
|
if (tstate & TSTATE_PRIV)
|
|
|
|
|
die_if_kernel("lddfmna from kernel", regs);
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (test_thread_flag(TIF_32BIT))
|
|
|
|
|
pc = (u32)pc;
|
|
|
|
|
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
2006-02-10 12:20:34 +08:00
|
|
|
int asi = decode_asi(insn, regs);
|
2009-01-09 08:52:36 +08:00
|
|
|
u32 first, second;
|
2009-01-08 09:15:57 +08:00
|
|
|
int err;
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if ((asi > ASI_SNFL) ||
|
|
|
|
|
(asi < ASI_P))
|
|
|
|
|
goto daex;
|
2009-01-09 08:52:36 +08:00
|
|
|
first = second = 0;
|
2009-01-08 09:15:57 +08:00
|
|
|
err = get_user(first, (u32 __user *)sfar);
|
|
|
|
|
if (!err)
|
|
|
|
|
err = get_user(second, (u32 __user *)(sfar + 4));
|
|
|
|
|
if (err) {
|
2009-01-09 08:52:36 +08:00
|
|
|
if (!(asi & 0x2))
|
2005-04-17 06:20:36 +08:00
|
|
|
goto daex;
|
2009-01-09 08:52:36 +08:00
|
|
|
first = second = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
save_and_clear_fpu();
|
|
|
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
|
|
|
value = (((u64)first) << 32) | second;
|
|
|
|
|
if (asi & 0x8) /* Little */
|
|
|
|
|
value = __swab64p(&value);
|
|
|
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
|
|
|
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
|
|
|
|
|
current_thread_info()->fpsaved[0] = FPRS_FEF;
|
|
|
|
|
current_thread_info()->gsr[0] = 0;
|
|
|
|
|
}
|
|
|
|
|
if (!(current_thread_info()->fpsaved[0] & flag)) {
|
|
|
|
|
if (freg < 32)
|
|
|
|
|
memset(f->regs, 0, 32*sizeof(u32));
|
|
|
|
|
else
|
|
|
|
|
memset(f->regs+32, 0, 32*sizeof(u32));
|
|
|
|
|
}
|
|
|
|
|
*(u64 *)(f->regs + freg) = value;
|
|
|
|
|
current_thread_info()->fpsaved[0] |= flag;
|
|
|
|
|
} else {
|
2006-02-10 12:20:34 +08:00
|
|
|
daex:
|
|
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, sfar, sfsr);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, sfsr, sfar);
|
2013-09-14 20:02:11 +08:00
|
|
|
goto out;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
advance(regs);
|
2013-09-14 20:02:11 +08:00
|
|
|
out:
|
|
|
|
|
exception_exit(prev_state);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
|
|
|
|
|
{
|
2013-09-14 20:02:11 +08:00
|
|
|
enum ctx_state prev_state = exception_enter();
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned long pc = regs->tpc;
|
|
|
|
|
unsigned long tstate = regs->tstate;
|
|
|
|
|
u32 insn;
|
|
|
|
|
u64 value;
|
2006-02-10 12:20:34 +08:00
|
|
|
u8 freg;
|
2005-04-17 06:20:36 +08:00
|
|
|
int flag;
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
|
|
|
|
|
if (tstate & TSTATE_PRIV)
|
|
|
|
|
die_if_kernel("stdfmna from kernel", regs);
|
2011-06-27 20:41:57 +08:00
|
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (test_thread_flag(TIF_32BIT))
|
|
|
|
|
pc = (u32)pc;
|
|
|
|
|
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
2006-02-10 12:20:34 +08:00
|
|
|
int asi = decode_asi(insn, regs);
|
2005-04-17 06:20:36 +08:00
|
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
|
|
|
value = 0;
|
|
|
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
|
|
|
if ((asi > ASI_SNFL) ||
|
|
|
|
|
(asi < ASI_P))
|
|
|
|
|
goto daex;
|
|
|
|
|
save_and_clear_fpu();
|
|
|
|
|
if (current_thread_info()->fpsaved[0] & flag)
|
|
|
|
|
value = *(u64 *)&f->regs[freg];
|
|
|
|
|
switch (asi) {
|
|
|
|
|
case ASI_P:
|
|
|
|
|
case ASI_S: break;
|
|
|
|
|
case ASI_PL:
|
|
|
|
|
case ASI_SL:
|
|
|
|
|
value = __swab64p(&value); break;
|
|
|
|
|
default: goto daex;
|
|
|
|
|
}
|
|
|
|
|
if (put_user (value >> 32, (u32 __user *) sfar) ||
|
|
|
|
|
__put_user ((u32)value, (u32 __user *)(sfar + 4)))
|
|
|
|
|
goto daex;
|
|
|
|
|
} else {
|
2006-02-10 12:20:34 +08:00
|
|
|
daex:
|
|
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
|
sun4v_data_access_exception(regs, sfar, sfsr);
|
|
|
|
|
else
|
|
|
|
|
spitfire_data_access_exception(regs, sfsr, sfar);
|
2013-09-14 20:02:11 +08:00
|
|
|
goto out;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
advance(regs);
|
2013-09-14 20:02:11 +08:00
|
|
|
out:
|
|
|
|
|
exception_exit(prev_state);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|