2009-08-06 21:25:28 +08:00
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/*
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* This file is part of wl1271
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*
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2010-03-26 18:53:21 +08:00
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* Copyright (C) 2008-2010 Nokia Corporation
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2009-08-06 21:25:28 +08:00
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/gpio.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2009-08-06 21:25:28 +08:00
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#include "wl1271_acx.h"
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#include "wl1271_reg.h"
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#include "wl1271_boot.h"
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2010-02-18 19:25:55 +08:00
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#include "wl1271_io.h"
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2009-08-06 21:25:28 +08:00
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#include "wl1271_event.h"
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static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
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[PART_DOWN] = {
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.mem = {
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.start = 0x00000000,
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.size = 0x000177c0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x00008800
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},
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2009-10-12 20:08:46 +08:00
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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2009-08-06 21:25:28 +08:00
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},
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[PART_WORK] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = REGISTERS_BASE,
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2009-10-12 20:08:46 +08:00
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.size = 0x0000a000
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},
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.mem2 = {
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.start = 0x003004f8,
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.size = 0x00000004
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},
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.mem3 = {
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.start = 0x00040404,
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.size = 0x00000000
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2009-08-06 21:25:28 +08:00
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},
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},
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[PART_DRPW] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = DRPW_BASE,
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.size = 0x00006000
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2009-10-12 20:08:46 +08:00
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},
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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2009-08-06 21:25:28 +08:00
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}
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}
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};
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static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
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{
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u32 cpu_ctrl;
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/* 10.5.0 run the firmware (I) */
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2010-02-18 19:25:55 +08:00
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cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
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2009-08-06 21:25:28 +08:00
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/* 10.5.1 run the firmware (II) */
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cpu_ctrl |= flag;
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2010-02-18 19:25:55 +08:00
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wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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2009-08-06 21:25:28 +08:00
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}
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static void wl1271_boot_fw_version(struct wl1271 *wl)
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{
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struct wl1271_static_data static_data;
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2010-02-18 19:25:55 +08:00
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wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
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false);
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2009-08-06 21:25:28 +08:00
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strncpy(wl->chip.fw_ver, static_data.fw_version,
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sizeof(wl->chip.fw_ver));
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/* make sure the string is NULL-terminated */
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wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
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}
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static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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size_t fw_data_len, u32 dest)
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{
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2009-10-12 20:08:46 +08:00
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struct wl1271_partition_set partition;
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2009-08-06 21:25:28 +08:00
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int addr, chunk_num, partition_limit;
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2009-10-09 02:56:32 +08:00
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u8 *p, *chunk;
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2009-08-06 21:25:28 +08:00
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/* whal_FwCtrl_LoadFwImageSm() */
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wl1271_debug(DEBUG_BOOT, "starting firmware upload");
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2009-08-11 16:58:27 +08:00
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wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
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fw_data_len, CHUNK_SIZE);
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2009-08-06 21:25:28 +08:00
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if ((fw_data_len % 4) != 0) {
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wl1271_error("firmware length not multiple of four");
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return -EIO;
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}
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2009-10-09 02:56:32 +08:00
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chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
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2009-10-13 17:47:57 +08:00
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if (!chunk) {
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2009-10-09 02:56:32 +08:00
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wl1271_error("allocation for firmware upload chunk failed");
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return -ENOMEM;
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}
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2009-10-12 20:08:46 +08:00
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memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
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partition.mem.start = dest;
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wl1271_set_partition(wl, &partition);
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2009-08-06 21:25:28 +08:00
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/* 10.1 set partition limit and chunk num */
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chunk_num = 0;
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partition_limit = part_table[PART_DOWN].mem.size;
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while (chunk_num < fw_data_len / CHUNK_SIZE) {
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/* 10.2 update partition, if needed */
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addr = dest + (chunk_num + 2) * CHUNK_SIZE;
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if (addr > partition_limit) {
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addr = dest + chunk_num * CHUNK_SIZE;
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partition_limit = chunk_num * CHUNK_SIZE +
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part_table[PART_DOWN].mem.size;
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2009-10-12 20:08:46 +08:00
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partition.mem.start = addr;
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wl1271_set_partition(wl, &partition);
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2009-08-06 21:25:28 +08:00
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}
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/* 10.3 upload the chunk */
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addr = dest + chunk_num * CHUNK_SIZE;
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p = buf + chunk_num * CHUNK_SIZE;
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2009-10-09 02:56:32 +08:00
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memcpy(chunk, p, CHUNK_SIZE);
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2009-08-06 21:25:28 +08:00
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wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
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p, addr);
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2010-02-18 19:25:55 +08:00
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wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
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2009-08-06 21:25:28 +08:00
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chunk_num++;
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}
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/* 10.4 upload the last chunk */
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addr = dest + chunk_num * CHUNK_SIZE;
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p = buf + chunk_num * CHUNK_SIZE;
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2009-10-09 02:56:32 +08:00
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memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
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2009-08-11 16:58:27 +08:00
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wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
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2009-08-06 21:25:28 +08:00
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fw_data_len % CHUNK_SIZE, p, addr);
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2010-02-18 19:25:55 +08:00
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wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
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2009-08-06 21:25:28 +08:00
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2009-10-09 02:56:32 +08:00
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kfree(chunk);
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2009-08-06 21:25:28 +08:00
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return 0;
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}
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static int wl1271_boot_upload_firmware(struct wl1271 *wl)
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{
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u32 chunks, addr, len;
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2009-10-13 17:47:57 +08:00
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int ret = 0;
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2009-08-06 21:25:28 +08:00
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u8 *fw;
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fw = wl->fw;
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2009-10-15 15:33:29 +08:00
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chunks = be32_to_cpup((__be32 *) fw);
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2009-08-06 21:25:28 +08:00
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fw += sizeof(u32);
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wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
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while (chunks--) {
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2009-10-15 15:33:29 +08:00
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addr = be32_to_cpup((__be32 *) fw);
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2009-08-06 21:25:28 +08:00
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fw += sizeof(u32);
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2009-10-15 15:33:29 +08:00
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len = be32_to_cpup((__be32 *) fw);
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2009-08-06 21:25:28 +08:00
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fw += sizeof(u32);
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if (len > 300000) {
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wl1271_info("firmware chunk too long: %u", len);
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return -EINVAL;
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}
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wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
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chunks, addr, len);
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2009-10-13 17:47:57 +08:00
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ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
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if (ret != 0)
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break;
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2009-08-06 21:25:28 +08:00
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fw += len;
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}
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2009-10-13 17:47:57 +08:00
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return ret;
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2009-08-06 21:25:28 +08:00
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}
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static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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{
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size_t nvs_len, burst_len;
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int i;
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u32 dest_addr, val;
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2010-02-18 19:25:42 +08:00
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u8 *nvs_ptr, *nvs_aligned;
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2009-08-06 21:25:28 +08:00
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2010-02-18 19:25:42 +08:00
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if (wl->nvs == NULL)
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2009-08-06 21:25:28 +08:00
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return -ENODEV;
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2009-12-11 21:40:53 +08:00
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/* only the first part of the NVS needs to be uploaded */
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2010-02-18 19:25:42 +08:00
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nvs_len = sizeof(wl->nvs->nvs);
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nvs_ptr = (u8 *)wl->nvs->nvs;
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2009-08-06 21:25:28 +08:00
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2010-03-18 18:26:39 +08:00
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/* update current MAC address to NVS */
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nvs_ptr[11] = wl->mac_addr[0];
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nvs_ptr[10] = wl->mac_addr[1];
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nvs_ptr[6] = wl->mac_addr[2];
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nvs_ptr[5] = wl->mac_addr[3];
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nvs_ptr[4] = wl->mac_addr[4];
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nvs_ptr[3] = wl->mac_addr[5];
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2009-08-06 21:25:28 +08:00
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/*
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* Layout before the actual NVS tables:
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* 1 byte : burst length.
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* 2 bytes: destination address.
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* n bytes: data to burst copy.
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*
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* This is ended by a 0 length, then the NVS tables.
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*/
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/* FIXME: Do we need to check here whether the LSB is 1? */
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while (nvs_ptr[0]) {
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burst_len = nvs_ptr[0];
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dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
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/* FIXME: Due to our new wl1271_translate_reg_addr function,
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we need to add the REGISTER_BASE to the destination */
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dest_addr += REGISTERS_BASE;
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/* We move our pointer to the data */
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nvs_ptr += 3;
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for (i = 0; i < burst_len; i++) {
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val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
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| (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
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wl1271_debug(DEBUG_BOOT,
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"nvs burst write 0x%x: 0x%x",
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dest_addr, val);
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2010-02-18 19:25:55 +08:00
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wl1271_write32(wl, dest_addr, val);
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2009-08-06 21:25:28 +08:00
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nvs_ptr += 4;
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dest_addr += 4;
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}
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}
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/*
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* We've reached the first zero length, the first NVS table
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|
|
|
* is 7 bytes further.
|
|
|
|
*/
|
|
|
|
nvs_ptr += 7;
|
2010-02-18 19:25:42 +08:00
|
|
|
nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
|
2009-08-06 21:25:28 +08:00
|
|
|
nvs_len = ALIGN(nvs_len, 4);
|
|
|
|
|
|
|
|
/* FIXME: The driver sets the partition here, but this is not needed,
|
|
|
|
since it sets to the same one as currently in use */
|
|
|
|
/* Now we must set the partition correctly */
|
2009-10-12 20:08:46 +08:00
|
|
|
wl1271_set_partition(wl, &part_table[PART_WORK]);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* Copy the NVS tables to a new block to ensure alignment */
|
2010-02-18 19:25:45 +08:00
|
|
|
/* FIXME: We jump 3 more bytes before uploading the NVS. It seems
|
|
|
|
that our NVS files have three extra zeros here. I'm not sure whether
|
|
|
|
the problem is in our NVS generation or we should really jumpt these
|
|
|
|
3 bytes here */
|
|
|
|
nvs_ptr += 3;
|
|
|
|
|
|
|
|
nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if
|
|
|
|
(!nvs_aligned) return -ENOMEM;
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* And finally we upload the NVS tables */
|
|
|
|
/* FIXME: In wl1271, we upload everything at once.
|
|
|
|
No endianness handling needed here?! The ref driver doesn't do
|
|
|
|
anything about it at this point */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
kfree(nvs_aligned);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
|
|
|
|
{
|
2010-02-22 14:38:22 +08:00
|
|
|
wl1271_enable_interrupts(wl);
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
|
|
|
|
WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
|
|
|
|
wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
|
2009-08-06 21:25:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl1271_boot_soft_reset(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
u32 boot_data;
|
|
|
|
|
|
|
|
/* perform soft reset */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* SOFT_RESET is self clearing */
|
|
|
|
timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
|
|
|
|
while (1) {
|
2010-02-18 19:25:55 +08:00
|
|
|
boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
|
2009-08-06 21:25:28 +08:00
|
|
|
wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
|
|
|
|
if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
|
|
/* 1.2 check pWhalBus->uSelfClearTime if the
|
|
|
|
* timeout was reached */
|
|
|
|
wl1271_error("soft reset timeout");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
udelay(SOFT_RESET_STALL_TIME);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable Rx/Tx */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ENABLE, 0x0);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* disable auto calibration on start*/
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, SPARE_A2, 0xffff);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wl1271_boot_run_firmware(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int loop, ret;
|
2010-04-28 14:50:02 +08:00
|
|
|
u32 chip_id, intr;
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
|
|
|
|
|
2010-02-18 19:25:55 +08:00
|
|
|
chip_id = wl1271_read32(wl, CHIP_ID_B);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
|
|
|
|
|
|
|
|
if (chip_id != wl->chip.id) {
|
|
|
|
wl1271_error("chip id doesn't match after firmware boot");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* wait for init to complete */
|
|
|
|
loop = 0;
|
|
|
|
while (loop++ < INIT_LOOP) {
|
|
|
|
udelay(INIT_LOOP_DELAY);
|
2010-04-28 14:50:02 +08:00
|
|
|
intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
2010-04-28 14:50:02 +08:00
|
|
|
if (intr == 0xffffffff) {
|
2009-08-06 21:25:28 +08:00
|
|
|
wl1271_error("error reading hardware complete "
|
|
|
|
"init indication");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
/* check that ACX_INTR_INIT_COMPLETE is enabled */
|
2010-04-28 14:50:02 +08:00
|
|
|
else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
|
|
|
|
WL1271_ACX_INTR_INIT_COMPLETE);
|
2009-08-06 21:25:28 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-29 19:20:04 +08:00
|
|
|
if (loop > INIT_LOOP) {
|
2009-08-06 21:25:28 +08:00
|
|
|
wl1271_error("timeout waiting for the hardware to "
|
|
|
|
"complete initialization");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get hardware config command mail box */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* get hardware config event mail box */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* set the working partition to its "running" mode offset */
|
2009-10-12 20:08:46 +08:00
|
|
|
wl1271_set_partition(wl, &part_table[PART_WORK]);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
|
|
|
|
wl->cmd_box_addr, wl->event_box_addr);
|
|
|
|
|
|
|
|
wl1271_boot_fw_version(wl);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* in case of full asynchronous mode the firmware event must be
|
|
|
|
* ready to receive event from the command mailbox
|
|
|
|
*/
|
|
|
|
|
2009-10-09 02:56:36 +08:00
|
|
|
/* unmask required mbox events */
|
|
|
|
wl->event_mask = BSS_LOSE_EVENT_ID |
|
2009-11-03 02:22:11 +08:00
|
|
|
SCAN_COMPLETE_EVENT_ID |
|
2010-03-26 18:53:20 +08:00
|
|
|
PS_REPORT_EVENT_ID |
|
2010-03-26 18:53:21 +08:00
|
|
|
JOIN_EVENT_COMPLETE_ID |
|
2010-04-09 16:07:30 +08:00
|
|
|
DISCONNECT_EVENT_COMPLETE_ID |
|
2010-07-08 22:50:00 +08:00
|
|
|
RSSI_SNR_TRIGGER_0_EVENT_ID |
|
|
|
|
PSPOLL_DELIVERY_FAILURE_EVENT_ID;
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
ret = wl1271_event_unmask(wl);
|
|
|
|
if (ret < 0) {
|
|
|
|
wl1271_error("EVENT mask setting failed");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
wl1271_event_mbox_config(wl);
|
|
|
|
|
|
|
|
/* firmware startup completed */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
|
|
|
|
{
|
2009-10-12 20:08:48 +08:00
|
|
|
u32 polarity;
|
2009-08-06 21:25:28 +08:00
|
|
|
|
2009-10-12 20:08:48 +08:00
|
|
|
polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* We use HIGH polarity, so unset the LOW bit */
|
|
|
|
polarity &= ~POLARITY_LOW;
|
2009-10-12 20:08:48 +08:00
|
|
|
wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-07 16:38:58 +08:00
|
|
|
static void wl1271_boot_hw_version(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
u32 fuse;
|
|
|
|
|
|
|
|
fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
|
|
|
|
fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
|
|
|
|
|
|
|
|
wl->hw_pg_ver = (s8)fuse;
|
|
|
|
}
|
|
|
|
|
2009-08-06 21:25:28 +08:00
|
|
|
int wl1271_boot(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
u32 tmp, clk, pause;
|
|
|
|
|
2010-05-07 16:38:58 +08:00
|
|
|
wl1271_boot_hw_version(wl);
|
|
|
|
|
2009-10-12 20:08:49 +08:00
|
|
|
if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
|
|
|
|
/* ref clk: 19.2/38.4/38.4-XTAL */
|
2009-08-06 21:25:28 +08:00
|
|
|
clk = 0x3;
|
|
|
|
else if (REF_CLOCK == 1 || REF_CLOCK == 3)
|
|
|
|
/* ref clk: 26/52 */
|
|
|
|
clk = 0x5;
|
|
|
|
|
2009-10-12 20:08:49 +08:00
|
|
|
if (REF_CLOCK != 0) {
|
|
|
|
u16 val;
|
2010-03-26 18:53:15 +08:00
|
|
|
/* Set clock type (open drain) */
|
2009-10-12 20:08:49 +08:00
|
|
|
val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
|
|
|
|
val &= FREF_CLK_TYPE_BITS;
|
|
|
|
wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
|
2010-03-26 18:53:15 +08:00
|
|
|
|
|
|
|
/* Set clock pull mode (no pull) */
|
|
|
|
val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
|
|
|
|
val |= NO_PULL;
|
|
|
|
wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
|
2009-10-12 20:08:49 +08:00
|
|
|
} else {
|
|
|
|
u16 val;
|
|
|
|
/* Set clock polarity */
|
|
|
|
val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
|
|
|
|
val &= FREF_CLK_POLARITY_BITS;
|
|
|
|
val |= CLK_REQ_OUTN_SEL;
|
|
|
|
wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
|
|
|
|
}
|
|
|
|
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, PLL_PARAMETERS, clk);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
2010-02-18 19:25:55 +08:00
|
|
|
pause = wl1271_read32(wl, PLL_PARAMETERS);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
|
|
|
|
|
|
|
|
pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
|
|
|
|
* WU_COUNTER_PAUSE_VAL instead of
|
|
|
|
* 0x3ff (magic number ). How does
|
|
|
|
* this work?! */
|
|
|
|
pause |= WU_COUNTER_PAUSE_VAL;
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* Continue the ELP wake up sequence */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
|
2009-08-06 21:25:28 +08:00
|
|
|
udelay(500);
|
|
|
|
|
2009-10-12 20:08:46 +08:00
|
|
|
wl1271_set_partition(wl, &part_table[PART_DRPW]);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* Read-modify-write DRPW_SCRATCH_START register (see next state)
|
|
|
|
to be used by DRPw FW. The RTRIM value will be added by the FW
|
|
|
|
before taking DRPw out of reset */
|
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
|
2010-02-18 19:25:55 +08:00
|
|
|
clk = wl1271_read32(wl, DRPW_SCRATCH_START);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
|
|
|
|
|
|
|
|
/* 2 */
|
|
|
|
clk |= (REF_CLOCK << 1) << 4;
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, DRPW_SCRATCH_START, clk);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
2009-10-12 20:08:46 +08:00
|
|
|
wl1271_set_partition(wl, &part_table[PART_WORK]);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* Disable interrupts */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
ret = wl1271_boot_soft_reset(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* 2. start processing NVS file */
|
|
|
|
ret = wl1271_boot_upload_nvs(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* write firmware's last address (ie. it's length) to
|
|
|
|
* ACX_EEPROMLESS_IND_REG */
|
|
|
|
wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
|
|
|
|
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
2010-02-18 19:25:55 +08:00
|
|
|
tmp = wl1271_read32(wl, CHIP_ID_B);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
|
|
|
|
|
|
|
|
/* 6. read the EEPROM parameters */
|
2010-02-18 19:25:55 +08:00
|
|
|
tmp = wl1271_read32(wl, SCR_PAD2);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
ret = wl1271_boot_write_irq_polarity(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* FIXME: Need to check whether this is really what we want */
|
2010-02-18 19:25:55 +08:00
|
|
|
wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
|
|
|
|
WL1271_ACX_ALL_EVENTS_VECTOR);
|
2009-08-06 21:25:28 +08:00
|
|
|
|
|
|
|
/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
|
|
|
|
* to upload_fw) */
|
|
|
|
|
|
|
|
ret = wl1271_boot_upload_firmware(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* 10.5 start firmware */
|
|
|
|
ret = wl1271_boot_run_firmware(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2009-10-13 17:47:45 +08:00
|
|
|
/* Enable firmware interrupts now */
|
|
|
|
wl1271_boot_enable_interrupts(wl);
|
|
|
|
|
2009-08-06 21:25:28 +08:00
|
|
|
/* set the wl1271 default filters */
|
|
|
|
wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
|
|
|
|
wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
|
|
|
|
|
|
|
|
wl1271_event_mbox_config(wl);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|